Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 6/20/2022
Public

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6.6.1. Single Global Reset Signal Implemented by Platform Designer

When you select System > Create Global Reset Network, the Platform Designer interconnect creates a global reset bus. All the reset requests are ORed together, synchronized to each clock domain, and fed to the reset inputs. The duration of the reset signal is at least one clock period.

The Platform Designer interconnect inserts the system‑wide reset under the following conditions:

  • The global reset input to the Platform Designer system is asserted.
  • Any component asserts its resetrequest signal.