Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 6/20/2022
Public

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7.8.2.2. Avalon® Packets to Transactions Converter IP Supported Transactions

The Avalon® Packets to Transactions Converter IP supports the following Avalon® memory mapped transactions:

Table 188.   Avalon® Packets to Transactions Converter IP Supported Transactions
Transaction Code Avalon® Memory Mapped Transaction Description
0x00 Write, non-incrementing address. Writes data to the address until the total number of bytes written to the same word address equals to the value specified in the size field.
0x04 Write, incrementing address. Writes transaction data starting at the current address.
0x10 Read, non-incrementing address. Reads 32 bits of data from the address until the total number of bytes read from the same address equals to the value specified in the size field.
0x14 Read, incrementing address. Reads the number of bytes specified in the size parameter starting from the current address.
0x7f No transaction. No transaction is initiated. You can use this transaction type for testing purposes. Although no transaction is initiated on the Avalon® memory mapped interface, the IP still returns a response packet for this transaction code.

The Avalon® Packets to Transactions Converter IP can process only a single transaction at a time. The ready signal on the IP Avalon® streaming sink interface is asserted only when the current transaction is completely processed.

No internal buffer is implemented on the datapaths. Data received on the Avalon® streaming interface is forwarded directly to the Avalon® memory mapped interface and vice-versa. Asserting the waitrequest signal on the Avalon® memory mapped interface backpressures the Avalon® streaming sink interface. In the opposite direction, if the Avalon® streaming source interface is backpressured, the read signal on the Avalon® memory mapped interface is not asserted until the backpressure is alleviated. Backpressuring the Avalon® streaming source in the middle of a read can result in data loss. In this cases, the IP returns the data that is successfully received.

A transaction is considered complete when the IP receives an EOP. For write transactions, the actual data size is expected to be the same as the value of the size property. Whether or not both values agree, the IP always uses the end of packet (EOP) to determine the end of data.