Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 6/20/2022
Public

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6.6.4.3.7. Reset Sequencer Software Reset Masking

Masking off (writing 1) to a reset_outN "Reset Mask Enable" signal prevents the corresponding reset from being asserted. Writing a bit to 0 to a reset mask enable signal allows assertion of reset_outN.
Table 93.  Values for the Reset Sequencer Software Reset Masking at Offset 0x18
Bit Attribute Default Description
31:10 Reserved.
9:0 RW 0 reset_outN "Reset Mask Enable"—This is a per-bit control to mask off the reset_outN bit. Software Reset Masking prevents the reset bit from being asserted during a reset assertion sequence. If reset_out is already asserted, it does not deassert the reset.