Visible to Intel only — GUID: mwh1409959064094
Ixiasoft
Visible to Intel only — GUID: mwh1409959064094
Ixiasoft
5.4. Inserting Pipeline Stages to Increase System Frequency
Platform Designer provides the Limit interconnect pipeline stages to option on the Interconnect Requirements tab to automatically add pipeline stages to the Platform Designer interconnect when you generate a system.
The Limit interconnect pipeline stages to parameter in the Interconnect Requirements tab allows you to define the maximum Avalon® streaming pipeline stages that Platform Designer can insert during generation. You can specify between 0 to 4 pipeline stages, where 0 means that the interconnect has a combinational datapath. You can specify a unique interconnect pipeline stage value for each subsystem.
For more information, refer to Interconnect Pipelining.