Intel® Cyclone® 10 LP FPGA Evaluation Kit User Guide

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ID 683580
Date 12/19/2019
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Evaluation Board Setup 4. Evaluation Board Components 5. Simple Socket Server 6. Board Test System A. Safety and Regulatory Information B. Additional Information
1. Overview x
1.1. Evaluation Kit Description 1.2. Recommended Operating Conditions 1.3. Handling the Board 1.4. Evaluation Board Revisions
1.1. Evaluation Kit Description x
1.1.1. Evaluation Board Description 1.1.2. Evaluation Kit Collateral 1.1.3. Power Supply Description
2. Getting Started x
2.1. Installing Quartus Prime Software 2.2. Installing the Evaluation Kit Collateral 2.3. Installing Intel® FPGA Download Cable Driver
3. Evaluation Board Setup x
3.1. Powering Up the Evaluation Board 3.2. Default Switch Settings 3.3. Recovering Factory Default Settings
4. Evaluation Board Components x
4.1. Board Overview 4.2. Intel® Cyclone® 10 LP FPGA Overview 4.3. MAX 10 System Controller Overview 4.4. FPGA Configuration 4.5. Status Elements 4.6. Setup Elements 4.7. General User Input/Output 4.8. Clocks 4.9. Connectors and Interfaces 4.10. Memory 4.11. System Power
4.4. FPGA Configuration x
4.4.1. Using the Quartus Prime Programmer 4.4.2. Program On-Board EPCQ or EPCQ-A Flash Memory 4.4.3. Active Serial Configuration
4.9. Connectors and Interfaces x
4.9.1. Gigabit Ethernet PHY 4.9.2. 2x20 GPIO Expansion Header 4.9.3. Arduino Connectors 4.9.4. Pmod Connectors
4.9.3. Arduino Connectors x
4.9.3.1. Digital IOs 4.9.3.2. Analog Inputs 4.9.3.3. Arduino Power
4.10. Memory x
4.10.1. HyperRAM 4.10.2. EPCQ or EPCQ-A Flash Memory
4.11. System Power x
4.11.1. Power Supply Options 4.11.2. Power Tree 4.11.3. Current Measurement
5. Simple Socket Server x
5.1. Connecting to the Simple Socket Server
6. Board Test System x
6.1. The Configure Menu 6.2. The System Info Tab 6.3. The GPIO Tab 6.4. The Flash Tab 6.5. The HyperRAM Tab 6.6. The Power Monitor 6.7. The Clock Control
A. Safety and Regulatory Information x
A.1. Safety Warnings A.2. Safety Cautions
B. Additional Information x
B.1. Revision History B.2. Compliance and Conformity Statements
1. Overview
2. Getting Started
3. Evaluation Board Setup
4. Evaluation Board Components
5. Simple Socket Server
6. Board Test System
A. Safety and Regulatory Information
B. Additional Information

4.9.4. Pmod Connectors

The Intel® Cyclone® 10 LP FPGA Evaluation Board features one Digilent Pmod™ Compatible header which is used to connect low frequency, low I/O pin count peripheral module.

The 12-pin version Pmod connector is chosen and this provides 8 I/O signal pins. The peripheral module interface also encompasses a variant using I2C interface and two or four wire MTE cables. The Pmod signals are connected to FPGA Bank 6.

Table 21.  Pmod Signals
Board Reference Schematic Signal Name Schematic Share Bus Signal Name FPGA Pin Number I/O Standard Direction @ FPGA Description
Pmod (J8) PMOD_D0 PMOD_IO0 D16 3.3 V IO Pmod IO 0
PMOD_D1 PMOD_IO1 F13 3.3 V IO Pmod IO 1
PMOD_D2 PMOD_IO2 D15 3.3 V IO Pmod IO 2
PMOD_D3 PMOD_IO3 F16 3.3 V IO Pmod IO 3
PMOD_D4 PMOD_IO4 C16 3.3 V IO Pmod IO 4
PMOD_D5 PMOD_IO5 F15 3.3 V IO Pmod IO 5
PMOD_D6 PMOD_IO6 C15 3.3 V IO Pmod IO 6
PMOD_D7 PMOD_IO7 B16 3.3 V IO Pmod IO 7

The Pmod specification does not specify module power consumption, but assumes no more than approximately 100 mA. On this board, the Pmod connector can offer up to 250 mA @ 3.3 V when the board is powered from external adapter connector (J12).

When using the Pmod module, the USB may not provide sufficient power. Intel recommends that you use an external adapter connector (J12) to power up the board.

Table 22.  Pmod Header Power Output Capability
Power Rail Output Pin Location Maximum Current Note
VCC_3.3 V J8.6, J8.12 0.25A

VCC_3.3 V output capability to Pmod module

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