Intel® Cyclone® 10 LP FPGA Evaluation Kit User Guide

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ID 683580
Date 12/19/2019
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Evaluation Board Setup 4. Evaluation Board Components 5. Simple Socket Server 6. Board Test System A. Safety and Regulatory Information B. Additional Information
1. Overview x
1.1. Evaluation Kit Description 1.2. Recommended Operating Conditions 1.3. Handling the Board 1.4. Evaluation Board Revisions
1.1. Evaluation Kit Description x
1.1.1. Evaluation Board Description 1.1.2. Evaluation Kit Collateral 1.1.3. Power Supply Description
2. Getting Started x
2.1. Installing Quartus Prime Software 2.2. Installing the Evaluation Kit Collateral 2.3. Installing Intel® FPGA Download Cable Driver
3. Evaluation Board Setup x
3.1. Powering Up the Evaluation Board 3.2. Default Switch Settings 3.3. Recovering Factory Default Settings
4. Evaluation Board Components x
4.1. Board Overview 4.2. Intel® Cyclone® 10 LP FPGA Overview 4.3. MAX 10 System Controller Overview 4.4. FPGA Configuration 4.5. Status Elements 4.6. Setup Elements 4.7. General User Input/Output 4.8. Clocks 4.9. Connectors and Interfaces 4.10. Memory 4.11. System Power
4.4. FPGA Configuration x
4.4.1. Using the Quartus Prime Programmer 4.4.2. Program On-Board EPCQ or EPCQ-A Flash Memory 4.4.3. Active Serial Configuration
4.9. Connectors and Interfaces x
4.9.1. Gigabit Ethernet PHY 4.9.2. 2x20 GPIO Expansion Header 4.9.3. Arduino Connectors 4.9.4. Pmod Connectors
4.9.3. Arduino Connectors x
4.9.3.1. Digital IOs 4.9.3.2. Analog Inputs 4.9.3.3. Arduino Power
4.10. Memory x
4.10.1. HyperRAM 4.10.2. EPCQ or EPCQ-A Flash Memory
4.11. System Power x
4.11.1. Power Supply Options 4.11.2. Power Tree 4.11.3. Current Measurement
5. Simple Socket Server x
5.1. Connecting to the Simple Socket Server
6. Board Test System x
6.1. The Configure Menu 6.2. The System Info Tab 6.3. The GPIO Tab 6.4. The Flash Tab 6.5. The HyperRAM Tab 6.6. The Power Monitor 6.7. The Clock Control
A. Safety and Regulatory Information x
A.1. Safety Warnings A.2. Safety Cautions
B. Additional Information x
B.1. Revision History B.2. Compliance and Conformity Statements
1. Overview
2. Getting Started
3. Evaluation Board Setup
4. Evaluation Board Components
5. Simple Socket Server
6. Board Test System
A. Safety and Regulatory Information
B. Additional Information

4.9.2. 2x20 GPIO Expansion Header

The Intel® Cyclone® 10 LP FPGA evaluation board provides one 40-pin expansion GPIO header with up to 36 GPIO signals. This 2x20 GPIO Header is compatible with some Terasic 2x20 GPIO cards.

There are also +5 V (VCC_5V_GPIO) and +3.3 V (VCC_3.3V) and two GND pins on 2x20 GPIO expansion header. All GPIO signals GPIO[0:35] are 3.3 V single-ended LVCMOS/LVTTL signals who are connected to Intel® Cyclone® 10 LP FPGA directly.

Table 15.  2X20 GPIO Header Signals
Board Reference Schematic Signal Name FPGA Pin Number I/O Standard Direction @ FPGA Description
J10.1 GPIO0 L13 3.3 V IO GPIO Signal 0
J10.2 GPIO1 L16 3.3 V IO GPIO Signal 1
J10.3 GPIO2 L15 3.3 V IO GPIO Signal 2
J10.4 GPIO3 K16 3.3 V IO GPIO Signal 3
J10.5 GPIO4 P16 3.3 V IO GPIO Signal 4
J10.6 GPIO5 R16 3.3 V IO GPIO Signal 5
J10.7 GPIO6 N16 3.3 V IO GPIO Signal 6
J10.8 GPIO7 N15 3.3 V IO GPIO Signal 7
J10.9 GPIO8 N14 3.3 V IO GPIO Signal 8
J10.10 GPIO9 P15 3.3 V IO GPIO Signal 9
J10.11 VCC_5V_GPIO --- --- --- Short to VCC_5V
J10.12 GND --- --- --- Ground
J10.13 GPIO10 N8 3.3 V IO GPIO Signal 10
J10.14 GPIO11 P8 3.3 V IO GPIO Signal 11
J10.15 GPIO12 M8 3.3 V IO GPIO Signal 12
J10.16 GPIO13 L8 3.3 V IO GPIO Signal 13
J10.17 GPIO14 R7 3.3 V IO GPIO Signal 14
J10.18 GPIO15 T7 3.3 V IO GPIO Signal 15
J10.19 GPIO16 L7 3.3 V IO GPIO Signal 16
J10.20 GPIO17 M7 3.3 V IO GPIO Signal 17
J10.21 GPIO18 R6 3.3 V IO GPIO Signal 18
J10.22 GPIO19 T6 3.3 V IO GPIO Signal 19
J10.23 GPIO20 T2 3.3 V IO GPIO Signal 20
J10.24 GPIO21 M6 3.3 V IO GPIO Signal 21
J10.25 GPIO22 R5 3.3 V IO GPIO Signal 22
J10.26 GPIO23 T5 3.3 V IO GPIO Signal 23
J10.27 GPIO24 N5 3.3 V IO GPIO Signal 24
J10.28 GPIO25 N6 3.3 V IO GPIO Signal 25
J10.29 VCC_3.3V --- --- --- VCC_3.3V
J10.30 GND --- --- --- Ground
J10.31 GPIO26 R4 3.3 V IO GPIO Signal 26
J10.32 GPIO27 T4 3.3 V IO GPIO Signal 27
J10.33 GPIO28 N3 3.3 V IO GPIO Signal 28
J10.34 GPIO29 P3 3.3 V IO GPIO Signal 29
J10.35 GPIO30 R3 3.3 V IO GPIO Signal 30
J10.36 GPIO31 T3 3.3 V IO GPIO Signal 31
J10.37 GPIO32 P6 3.3 V IO GPIO Signal 32
J10.38 GPIO33 P2 3.3 V IO GPIO Signal 33
J10.39 GPIO34 P1 3.3 V IO GPIO Signal 34
J10.40 GPIO35 R1 3.3 V IO GPIO Signal 35
Figure 8. GPIO

The maximum power output capability is shown in the table below. When using 2x20 GPIO Header, USB may not provide sufficient power. Hence, use an external adapter connector (J12) to power up the board.

Table 16.  2X20 GPIO Header Power Output Capability
PowerRail Output Pin Location Max Current Note
VCC_5V_GPIO J10.11 0.5 A VCC_5V output capability to card (depends on the power adapter capability)
VCC_3.3V J10.29 0.5 A VCC_3.3V output capability to daughter card
Level Two Title