Intel® Cyclone® 10 LP FPGA Evaluation Kit User Guide

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ID 683580
Date 12/19/2019
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Evaluation Board Setup 4. Evaluation Board Components 5. Simple Socket Server 6. Board Test System A. Safety and Regulatory Information B. Additional Information
1. Overview x
1.1. Evaluation Kit Description 1.2. Recommended Operating Conditions 1.3. Handling the Board 1.4. Evaluation Board Revisions
1.1. Evaluation Kit Description x
1.1.1. Evaluation Board Description 1.1.2. Evaluation Kit Collateral 1.1.3. Power Supply Description
2. Getting Started x
2.1. Installing Quartus Prime Software 2.2. Installing the Evaluation Kit Collateral 2.3. Installing Intel® FPGA Download Cable Driver
3. Evaluation Board Setup x
3.1. Powering Up the Evaluation Board 3.2. Default Switch Settings 3.3. Recovering Factory Default Settings
4. Evaluation Board Components x
4.1. Board Overview 4.2. Intel® Cyclone® 10 LP FPGA Overview 4.3. MAX 10 System Controller Overview 4.4. FPGA Configuration 4.5. Status Elements 4.6. Setup Elements 4.7. General User Input/Output 4.8. Clocks 4.9. Connectors and Interfaces 4.10. Memory 4.11. System Power
4.4. FPGA Configuration x
4.4.1. Using the Quartus Prime Programmer 4.4.2. Program On-Board EPCQ or EPCQ-A Flash Memory 4.4.3. Active Serial Configuration
4.9. Connectors and Interfaces x
4.9.1. Gigabit Ethernet PHY 4.9.2. 2x20 GPIO Expansion Header 4.9.3. Arduino Connectors 4.9.4. Pmod Connectors
4.9.3. Arduino Connectors x
4.9.3.1. Digital IOs 4.9.3.2. Analog Inputs 4.9.3.3. Arduino Power
4.10. Memory x
4.10.1. HyperRAM 4.10.2. EPCQ or EPCQ-A Flash Memory
4.11. System Power x
4.11.1. Power Supply Options 4.11.2. Power Tree 4.11.3. Current Measurement
5. Simple Socket Server x
5.1. Connecting to the Simple Socket Server
6. Board Test System x
6.1. The Configure Menu 6.2. The System Info Tab 6.3. The GPIO Tab 6.4. The Flash Tab 6.5. The HyperRAM Tab 6.6. The Power Monitor 6.7. The Clock Control
A. Safety and Regulatory Information x
A.1. Safety Warnings A.2. Safety Cautions
B. Additional Information x
B.1. Revision History B.2. Compliance and Conformity Statements
1. Overview
2. Getting Started
3. Evaluation Board Setup
4. Evaluation Board Components
5. Simple Socket Server
6. Board Test System
A. Safety and Regulatory Information
B. Additional Information

4.10.2. EPCQ or EPCQ-A Flash Memory

The Intel® Cyclone® 10 LP FPGA Evaluation board has an Intel® 64 Mb EPCQ64 or 128 Mb EPCQ128A in-system programmable NOR flash for non-volatile storage of the FPGA configuration data, board information, test application data and user code space.

Depending on its revision, your board has one of two flash memory devices: EPCQ64 or EPCQ128A. To determine which device you have, refer to "Evaluation Board Revisions".

Although the quad-serial flash provided has a ×4 data width, the evaluation board has a ×1 data width because the Intel® Cyclone® 10 LP FPGA only supports an AS ×1 configuration scheme. Other data signals are tied to 3.3 V power required by the device datasheet.

The table below shows the memory map for this flash memory. This memory provides non-volatile storage for FPGA bit stream, Nios® II factory software and other information.

Table 25.  Flash Memory Map
Block Description Size (KB) Address Comments
Board Test System Scratch 512 0x0073.0000 - 0x007A.FFFF BTS System Testing
Board Information 64 0x0072.0000 - 0x0072.FFFF Board Information
Ethernet Option Bits 64 0x0071.0000 - 0x0071.FFFF MAC Address Information
User Design Reset Vector 64 0x0070.0000 - 0x0070.FFFF Nios II Reset Vector Information
Factory Software (ELF) 4096 0x0030.0000 - 0x006F.FFFF Software File
Factory Hardware (sof) 3072 0x0000.0000 - 0x002F.FFFF SOF File
Total 7872    

The signal connections between the Intel® Cyclone® 10 LP FPGA and flash comply with the AS ×1 configuration requirements.

Table 26.  Signal Connections
Flash Pin Number Schematic Signal Name FPGA Pin Number I/O Standard Description
U2.16 C10_AS_DCLK U1.H1 3.3 V FPGA Clock Output
U2.7 C10_AS_CSn U1.D2 3.3 V FPGA Chip Select Output
U2.8 C10_AS_DATA0 U1.H2 3.3 V FPGA Data Input
U2.15 C10_AS_ASDO U1.C1 3.3 V FPGA Data and Control Signals Output
Note: When using a serial flash loader (SFL) core and the Intel® Quartus® Prime Programmer to erase and program the flash, virtual JTAG must be bypassed by setting the SW1.4 switch to ON. Signal Net VTAP_BYPASSn is logic 0.
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