Intel® Cyclone® 10 LP FPGA Evaluation Kit User Guide

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ID 683580
Date 12/19/2019
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Evaluation Board Setup 4. Evaluation Board Components 5. Simple Socket Server 6. Board Test System A. Safety and Regulatory Information B. Additional Information
1. Overview x
1.1. Evaluation Kit Description 1.2. Recommended Operating Conditions 1.3. Handling the Board 1.4. Evaluation Board Revisions
1.1. Evaluation Kit Description x
1.1.1. Evaluation Board Description 1.1.2. Evaluation Kit Collateral 1.1.3. Power Supply Description
2. Getting Started x
2.1. Installing Quartus Prime Software 2.2. Installing the Evaluation Kit Collateral 2.3. Installing Intel® FPGA Download Cable Driver
3. Evaluation Board Setup x
3.1. Powering Up the Evaluation Board 3.2. Default Switch Settings 3.3. Recovering Factory Default Settings
4. Evaluation Board Components x
4.1. Board Overview 4.2. Intel® Cyclone® 10 LP FPGA Overview 4.3. MAX 10 System Controller Overview 4.4. FPGA Configuration 4.5. Status Elements 4.6. Setup Elements 4.7. General User Input/Output 4.8. Clocks 4.9. Connectors and Interfaces 4.10. Memory 4.11. System Power
4.4. FPGA Configuration x
4.4.1. Using the Quartus Prime Programmer 4.4.2. Program On-Board EPCQ or EPCQ-A Flash Memory 4.4.3. Active Serial Configuration
4.9. Connectors and Interfaces x
4.9.1. Gigabit Ethernet PHY 4.9.2. 2x20 GPIO Expansion Header 4.9.3. Arduino Connectors 4.9.4. Pmod Connectors
4.9.3. Arduino Connectors x
4.9.3.1. Digital IOs 4.9.3.2. Analog Inputs 4.9.3.3. Arduino Power
4.10. Memory x
4.10.1. HyperRAM 4.10.2. EPCQ or EPCQ-A Flash Memory
4.11. System Power x
4.11.1. Power Supply Options 4.11.2. Power Tree 4.11.3. Current Measurement
5. Simple Socket Server x
5.1. Connecting to the Simple Socket Server
6. Board Test System x
6.1. The Configure Menu 6.2. The System Info Tab 6.3. The GPIO Tab 6.4. The Flash Tab 6.5. The HyperRAM Tab 6.6. The Power Monitor 6.7. The Clock Control
A. Safety and Regulatory Information x
A.1. Safety Warnings A.2. Safety Cautions
B. Additional Information x
B.1. Revision History B.2. Compliance and Conformity Statements
1. Overview
2. Getting Started
3. Evaluation Board Setup
4. Evaluation Board Components
5. Simple Socket Server
6. Board Test System
A. Safety and Regulatory Information
B. Additional Information

4.9.1. Gigabit Ethernet PHY

The evaluation board supports single port Ethernet through Intel XWAY PHY11G PEF7071 Ethernet PHY chips. This physical layer device has general applications using RJ-45 connector.

Figure 7. MAC-to-PHY connection by PEF7071 device

Specific to the Intel® Cyclone® 10 LP FPGA evaluation board, the MAC-to-PHY interface is configured to a RGMII interface connection with MDIO interface as management.

Table 14.  Ethernet PHY Table
Schematic Signal Name Schematic Shared Bus Signal Name FPGA Pin Number I/O Standard Direction @ FPGA Description
ENET_RG_TXCLK C10_RG_TXCLK D3 3.3 V Out RGMII TX clock
ENET_RG_TXD0 C10_RG_TXD0 E6 3.3 V Out RGMII TX data 0
ENET_RG_TXD1 C10_RG_TXD1 A3 3.3 V Out RGMII TX data 1
ENET_RG_TXD2 C10_RG_TXD2 B3 3.3 V Out RGMII TX data 2
ENET_RG_TXD3 C10_RG_TXD3 A2 3.3 V Out RGMII TX data 3
ENET_RG_TXCTL C10_RG_TXCTL D6 3.3 V Out RGMII TX control
ENET_RG_RXCLK RG_RXCLK B8 3.3 V In RGMII RX Clock
ENET_RG_RXD0 RG_RXD0 A7 3.3 V In RGMII RX data 0
ENET_RG_RXD1 RG_RXD1 B7 3.3 V In RGMII RX data 1
ENET_RG_RXD2 RG_RXD2 A6 3.3 V In RGMII RX data 2
ENET_EG_RXD3 RG_RXD3 B6 3.3 V In RGMII RX data 3
ENET_RG_RXCTL RG_RXCTL A5 3.3 V In RGMII RX Control
ENET_INT   B5 3.3 V In Management Interrupt
ENET_MDC   B4 3.3 V Out MDIO clock
ENET_MDIO   A4 3.3 V I/O MDIO data
ENET_RSTn   C6 3.3 V Out Device Reset
ENET_XTAL1          
ENET_XTAL2          
ENET_LED0     3.3 V Out Status LED0, Green
ENET_LED1     3.3 V Out Status LED1, Green
ENET_LED2     3.3 V Out Status LED2, Green
TPIAP         Twisted-Pair A, positive
TPIAN         Twisted-Pair A, negative
TPIBP         Twisted-Pair B, positive
TPIBN         Twisted-Pair B, negative
TPICP         Twisted-Pair C, positive
TPICN         Twisted-Pair C, negative
TPIDP         Twisted-Pair D, positive
TPIDN         Twisted-Pair D, negative
Note: 10/100/1000 Ethernet is supported beginning with the Intel® Quartus® Prime v17.1 software release.
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