Intel® Cyclone® 10 LP FPGA Evaluation Kit User Guide

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ID 683580
Date 12/19/2019
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Evaluation Board Setup 4. Evaluation Board Components 5. Simple Socket Server 6. Board Test System A. Safety and Regulatory Information B. Additional Information
1. Overview x
1.1. Evaluation Kit Description 1.2. Recommended Operating Conditions 1.3. Handling the Board 1.4. Evaluation Board Revisions
1.1. Evaluation Kit Description x
1.1.1. Evaluation Board Description 1.1.2. Evaluation Kit Collateral 1.1.3. Power Supply Description
2. Getting Started x
2.1. Installing Quartus Prime Software 2.2. Installing the Evaluation Kit Collateral 2.3. Installing Intel® FPGA Download Cable Driver
3. Evaluation Board Setup x
3.1. Powering Up the Evaluation Board 3.2. Default Switch Settings 3.3. Recovering Factory Default Settings
4. Evaluation Board Components x
4.1. Board Overview 4.2. Intel® Cyclone® 10 LP FPGA Overview 4.3. MAX 10 System Controller Overview 4.4. FPGA Configuration 4.5. Status Elements 4.6. Setup Elements 4.7. General User Input/Output 4.8. Clocks 4.9. Connectors and Interfaces 4.10. Memory 4.11. System Power
4.4. FPGA Configuration x
4.4.1. Using the Quartus Prime Programmer 4.4.2. Program On-Board EPCQ or EPCQ-A Flash Memory 4.4.3. Active Serial Configuration
4.9. Connectors and Interfaces x
4.9.1. Gigabit Ethernet PHY 4.9.2. 2x20 GPIO Expansion Header 4.9.3. Arduino Connectors 4.9.4. Pmod Connectors
4.9.3. Arduino Connectors x
4.9.3.1. Digital IOs 4.9.3.2. Analog Inputs 4.9.3.3. Arduino Power
4.10. Memory x
4.10.1. HyperRAM 4.10.2. EPCQ or EPCQ-A Flash Memory
4.11. System Power x
4.11.1. Power Supply Options 4.11.2. Power Tree 4.11.3. Current Measurement
5. Simple Socket Server x
5.1. Connecting to the Simple Socket Server
6. Board Test System x
6.1. The Configure Menu 6.2. The System Info Tab 6.3. The GPIO Tab 6.4. The Flash Tab 6.5. The HyperRAM Tab 6.6. The Power Monitor 6.7. The Clock Control
A. Safety and Regulatory Information x
A.1. Safety Warnings A.2. Safety Cautions
B. Additional Information x
B.1. Revision History B.2. Compliance and Conformity Statements
1. Overview
2. Getting Started
3. Evaluation Board Setup
4. Evaluation Board Components
5. Simple Socket Server
6. Board Test System
A. Safety and Regulatory Information
B. Additional Information

4.10.1. HyperRAM

HyperRAM is a portfolio of high-speed, low-pin-count memory product that uses the HyperBus interface technology. The Intel® Cyclone® 10 LP FPGA Evaluation Board supports HyperRAM with HyperBus Controller (HBMC) IP provided by Synaptic Labs.

One of the following HyperRAM parts is used:

  • ISSI IS66WVH16M8ALL-166B1LI
  • Cypress S70KS1281DPBHI020

HyperRAM is organized by 16M words x 8 bits with 1.8 V interface.

Table 23.  HyperRAM Signals List
Schematic Signal Name FPGA Pin Number I/O Standard Direction @ FPGA Description
HBUS_DQ7 R13 1.8 V IO Data Input/Output Bit 7
HBUS_DQ6 R12 1.8 V IO Data Input/Output Bit 6
HBUS_DQ5 R11 1.8 V IO Data Input/Output Bit 5
HBUS_DQ4 T10 1.8 V IO Data Input/Output Bit 4
HBUS_DQ3 R10 1.8 V IO Data Input/Output Bit 3
HBUS_DQ2 T11 1.8 V IO Data Input/Output Bit 2
HBUS_DQ1 T13 1.8 V IO Data Input/Output Bit 1
HBUS_DQ0 T12 1.8 V IO Data Input/Output Bit 0
HBUS_CKp P14 1.8 V OUT Differential Clock, Positive Node
HBUS_CKn R14 1.8 V OUT Differential Clock, Negative Node
HBUS_CS2n P9 1.8 V OUT Chip Select for HyperRAM
HBUS_RWDS T14 1.8 V IO Read Write Data Strobe
HBUS_RSTn N9 1.8 V OUT Hardware Reset
HBUS_CS1n N12 1.8 V OUT Chip Select for Hyper FLASH (Reserved Only)
HBUS_RSTOn T15 1.8 V IN Reset Output from slave to master (Reserved Only)
HBUS_INTn P11 1.8 V IN Interrupt Output from slave to master (Reserved Only)
Note: The Synaptic Labs HyperBus® Memory Controller IP (HBMC) for Intel FPGA is available in a Basic Edition (OpenCore) and a Full Edition. The differences are listed in the following table.
Table 24.  HBMC Features by Edition
  Basic Edition Full Edition
License required Trial license Node-locked license
.sof file supports conversion to other formats No Yes
.sof file runs on the BTS No Yes
Burst lengths supported 1 or 8 1, 2, 4, 8, 16, 32, 64 or 128
Note: Contact Synaptic Labs to download the HBMC license and the latest version of the HBMC IP.
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