Intel® Cyclone® 10 LP FPGA Evaluation Kit User Guide

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ID 683580
Date 12/19/2019
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Evaluation Board Setup 4. Evaluation Board Components 5. Simple Socket Server 6. Board Test System A. Safety and Regulatory Information B. Additional Information
1. Overview x
1.1. Evaluation Kit Description 1.2. Recommended Operating Conditions 1.3. Handling the Board 1.4. Evaluation Board Revisions
1.1. Evaluation Kit Description x
1.1.1. Evaluation Board Description 1.1.2. Evaluation Kit Collateral 1.1.3. Power Supply Description
2. Getting Started x
2.1. Installing Quartus Prime Software 2.2. Installing the Evaluation Kit Collateral 2.3. Installing Intel® FPGA Download Cable Driver
3. Evaluation Board Setup x
3.1. Powering Up the Evaluation Board 3.2. Default Switch Settings 3.3. Recovering Factory Default Settings
4. Evaluation Board Components x
4.1. Board Overview 4.2. Intel® Cyclone® 10 LP FPGA Overview 4.3. MAX 10 System Controller Overview 4.4. FPGA Configuration 4.5. Status Elements 4.6. Setup Elements 4.7. General User Input/Output 4.8. Clocks 4.9. Connectors and Interfaces 4.10. Memory 4.11. System Power
4.4. FPGA Configuration x
4.4.1. Using the Quartus Prime Programmer 4.4.2. Program On-Board EPCQ or EPCQ-A Flash Memory 4.4.3. Active Serial Configuration
4.9. Connectors and Interfaces x
4.9.1. Gigabit Ethernet PHY 4.9.2. 2x20 GPIO Expansion Header 4.9.3. Arduino Connectors 4.9.4. Pmod Connectors
4.9.3. Arduino Connectors x
4.9.3.1. Digital IOs 4.9.3.2. Analog Inputs 4.9.3.3. Arduino Power
4.10. Memory x
4.10.1. HyperRAM 4.10.2. EPCQ or EPCQ-A Flash Memory
4.11. System Power x
4.11.1. Power Supply Options 4.11.2. Power Tree 4.11.3. Current Measurement
5. Simple Socket Server x
5.1. Connecting to the Simple Socket Server
6. Board Test System x
6.1. The Configure Menu 6.2. The System Info Tab 6.3. The GPIO Tab 6.4. The Flash Tab 6.5. The HyperRAM Tab 6.6. The Power Monitor 6.7. The Clock Control
A. Safety and Regulatory Information x
A.1. Safety Warnings A.2. Safety Cautions
B. Additional Information x
B.1. Revision History B.2. Compliance and Conformity Statements
1. Overview
2. Getting Started
3. Evaluation Board Setup
4. Evaluation Board Components
5. Simple Socket Server
6. Board Test System
A. Safety and Regulatory Information
B. Additional Information

4.3. MAX 10 System Controller Overview

The highlights of the Intel® MAX® 10 devices include:
  • Internally stored dual configuration flash
  • User flash memory
  • Instant on support
  • Integrated analog-to-digital converter (ADC)
  • Single-chip Nios II soft core processor support

Intel® MAX® 10 devices are the ideal solution for system management, I/O expansion, communication control planes, industrial, automotive, and consumer applications.

Table 7.   Summary of Features for Intel® MAX® 10 Devices
Feature Description
Technology 55 nm TSMC Embedded Flash (Flash + SRAM) process technology
Packaging
  • Low cost, small form factor packages—support multiple packaging technologies and pin pitches
  • Multiple device densities with compatible package footprints for seamless migration between different device densities
  • RoHS6-compliant
Core architecture
  • 4-input look-up table (LUT) and single register logic element (LE)
  • LEs arranged in logic array block (LAB)
  • Embedded RAM and user flash memory
  • Clocks and PLLs
  • Embedded multiplier blocks
  • General purpose I/Os
Internal memory blocks
  • M9K—9 kilobits (Kb) memory blocks
  • Cascadable blocks to create RAM, dual port, and FIFO functions
User flash memory (UFM)
  • User accessible non-volatile storage
  • High speed operating frequency
  • Large memory size
  • High data retention
  • Multiple interface option
Embedded multiplier blocks
  • One 18 × 18 or two 9 × 9 multiplier modes
  • Cascadable blocks enabling creation of filters, arithmetic functions, and image processing pipelines
ADC
  • 12-bit successive approximation register (SAR) type
  • Up to 16 analog inputs
  • Cumulative speed up to 1 million samples per second (MSPS)
  • Integrated temperature sensing capability
Clock networks
  • Global clocks support
  • High speed frequency in clock network
Internal oscillator Built-in internal ring oscillator
PLLs
  • Analog-based
  • Low jitter
  • High precision clock synthesis
  • Clock delay compensation
  • Zero delay buffering
  • Multiple output taps
General-purpose I/Os (GPIOs)
  • Multiple I/O standards support
  • On-chip termination (OCT)
  • Up to 830 megabits per second (Mbps) LVDS receiver, 800 Mbps LVDS transmitter
External memory interface (EMIF) Supports up to 600 Mbps external memory interfaces:
  • DDR3, DDR3L, DDR2, LPDDR2
  • SRAM (Hardware support only)
Note: For 600 Mbps performance, –6 device speed grade is required. Performance varies according to device grade (commercial, industrial, or automotive) and device speed grade (–6 or –7). Refer to the MAX 10 Device Data Sheet or External Memory Interface Spec Estimator for more details.
Configuration
  • Internal configuration
  • JTAG
  • Advanced Encryption Standard (AES) 128-bit encryption and compression options
  • Flash memory data retention of 20 years at 85 °C
Flexible power supply schemes
  • Single- and dual-supply device options
  • Dynamically controlled input buffer power down
  • Sleep mode for dynamic power reduction
Related Information
Level Two Title