Intel® Cyclone® 10 LP FPGA Evaluation Kit User Guide

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ID 683580
Date 12/19/2019
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Evaluation Board Setup 4. Evaluation Board Components 5. Simple Socket Server 6. Board Test System A. Safety and Regulatory Information B. Additional Information
1. Overview x
1.1. Evaluation Kit Description 1.2. Recommended Operating Conditions 1.3. Handling the Board 1.4. Evaluation Board Revisions
1.1. Evaluation Kit Description x
1.1.1. Evaluation Board Description 1.1.2. Evaluation Kit Collateral 1.1.3. Power Supply Description
2. Getting Started x
2.1. Installing Quartus Prime Software 2.2. Installing the Evaluation Kit Collateral 2.3. Installing Intel® FPGA Download Cable Driver
3. Evaluation Board Setup x
3.1. Powering Up the Evaluation Board 3.2. Default Switch Settings 3.3. Recovering Factory Default Settings
4. Evaluation Board Components x
4.1. Board Overview 4.2. Intel® Cyclone® 10 LP FPGA Overview 4.3. MAX 10 System Controller Overview 4.4. FPGA Configuration 4.5. Status Elements 4.6. Setup Elements 4.7. General User Input/Output 4.8. Clocks 4.9. Connectors and Interfaces 4.10. Memory 4.11. System Power
4.4. FPGA Configuration x
4.4.1. Using the Quartus Prime Programmer 4.4.2. Program On-Board EPCQ or EPCQ-A Flash Memory 4.4.3. Active Serial Configuration
4.9. Connectors and Interfaces x
4.9.1. Gigabit Ethernet PHY 4.9.2. 2x20 GPIO Expansion Header 4.9.3. Arduino Connectors 4.9.4. Pmod Connectors
4.9.3. Arduino Connectors x
4.9.3.1. Digital IOs 4.9.3.2. Analog Inputs 4.9.3.3. Arduino Power
4.10. Memory x
4.10.1. HyperRAM 4.10.2. EPCQ or EPCQ-A Flash Memory
4.11. System Power x
4.11.1. Power Supply Options 4.11.2. Power Tree 4.11.3. Current Measurement
5. Simple Socket Server x
5.1. Connecting to the Simple Socket Server
6. Board Test System x
6.1. The Configure Menu 6.2. The System Info Tab 6.3. The GPIO Tab 6.4. The Flash Tab 6.5. The HyperRAM Tab 6.6. The Power Monitor 6.7. The Clock Control
A. Safety and Regulatory Information x
A.1. Safety Warnings A.2. Safety Cautions
B. Additional Information x
B.1. Revision History B.2. Compliance and Conformity Statements
1. Overview
2. Getting Started
3. Evaluation Board Setup
4. Evaluation Board Components
5. Simple Socket Server
6. Board Test System
A. Safety and Regulatory Information
B. Additional Information

6. Board Test System

The evaluation kit collateral includes an application called the Board Test System (BTS). The BTS provides an easy-to-use interface to alter the functional settings and observe the results. You can use the BTS to test board components, modify functional parameters, observe performance and measure power usage. While using the BTS, you can reconfigure the FPGA several times with test designs specific to the functionality you are testing.

Figure 16. Board Test System (BTS) Graphical User Interface (GUI)

Several designs are provided to test major board features. Each design provides data for one or more tabs in the application. The Configure menu identifies the appropriate design to download to the FPGA for each tab.

After successful FPGA configuration, the appropriate tab appears that allows you to exercise the related board features. Highlights appear in the board picture around the corresponding components.

The BTS communicates over the JTAG bus to a test design running in the FPGA. The BTS and Power Monitor share the JTAG bus with other applications like the Nios II debugger and the Signal Tap Embedded Logic Analyzer. As the Intel® Quartus® Prime uses most of the bandwidth of the JTAG bus, other applications using the JTAG bus might time-out.

Note: Close other applications before attempting to reconfigure the FPGA using the Intel® Quartus® Prime Programmer.

Section Content
The Configure Menu
The System Info Tab
The GPIO Tab
The Flash Tab
The HyperRAM Tab
The Power Monitor
The Clock Control

Level Two Title