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3.3.1. Project Creation
3.3.2. Design Entry
3.3.3. IP Status
3.3.4. Design Constraints
3.3.5. Synthesis
3.3.6. Design Implementation
3.3.7. Finalize Pinout
3.3.8. Viewing and Editing Design Placement
3.3.9. Static Timing Analysis
3.3.10. Generation of Device Programming Files
3.3.11. Power Analysis
3.3.12. Simulation
3.3.13. Hardware Verification
3.3.14. View Netlist
3.3.15. Design Optimization
3.3.16. Techniques to Improve Productivity
3.3.17. Cross-Probing in the Intel® Quartus® Prime Pro Edition Software
4.2.1.2.1. Memory Mode
4.2.1.2.2. Clocking Mode
4.2.1.2.3. Write and Read Operation Triggering
4.2.1.2.4. Read-During-Write Operation at the Same Address
4.2.1.2.5. Error Correction Code (ECC)
4.2.1.2.6. Byte Enable
4.2.1.2.7. Address Clock Enable
4.2.1.2.8. Parity Bit Support
4.2.1.2.9. Memory Initialization
4.2.1.2.10. Output Synchronous Set/Reset
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4.3.3.1. set_clock_groups
In the Xilinx* Vivado* software, the set_clock_groups constraint supports an additional switch named include_generated_clocks, to include generated clocks of a specific member in a clock group. However, in Intel® Quartus® Prime Pro Edition, you must add the generated clocks by name.
Example XDC command:
# Assign adc_clk, clocks generated from adc_clk and sys_clk, clocks generated from sys_clk to different clock groups
set_clock_groups -asynchronous \
-group [get_clocks -include_generated_clocks adc_clk] \
-group [get_clocks -include_generated_clocks sys_clk]
Equivalent SDC command:
# Assign adc_clk, clocks generated from adc_clk and sys_clk, clocks generated from sys_clk to different clock groups
set_clock_groups -asynchronous \
-group [get_clocks {adc_clk \
the_adc_pll|
Intel®
FPGA IOPLL_component_autogenerated|pll|clk[0] \
the_adc_pll|
Intel®
FPGA IOPLL_component_autogenerated|pll|clk[1] \
the_adc_pll|
Intel®
FPGA IOPLL_component_autogenerated|pll|clk[2] \
}] \
-group [get_clock {sys_clk \
the_system_pll|
Intel®
FPGA IOPLL_component_autogenerated|pll|clk[0] \
the_system_pll|
Intel®
FPGA IOPLL_component_autogenerated|pll|clk[1] \
} ]