AN 307: Intel® FPGA Design Flow for Xilinx* Users

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ID 683562
Date 3/20/2018
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Document Table of Contents
Document Table of Contents x
1. Introduction to Intel® FPGA Design Flow for Xilinx* Users 2. Technology Comparison 3. FPGA Tools Comparison 4. Xilinx* to Intel® FPGA Design Conversion 5. Conclusion 6. Document Revision History for Intel® FPGA Design Flow for Xilinx* Users
2. Technology Comparison x
2.1. Intel® FPGAs 2.2. Xilinx* FPGAs 2.3. Comparison Table 2.4. Intel® FPGA Device Features
3. FPGA Tools Comparison x
3.1. Hardware and Software Tools for FPGA Design 3.2. FPGA Design Flow Using Command Line Scripting 3.3. FPGA Design Flow Using Tools with GUIs 3.4. Additional Intel® Quartus® Prime Pro Edition Features
3.2. FPGA Design Flow Using Command Line Scripting x
3.2.1. Command-Line Executable Equivalents 3.2.2. Programming and Configuration File Support in the Intel® Quartus® Prime Pro Edition Software
3.2.1. Command-Line Executable Equivalents x
3.2.1.1. synth_design 3.2.1.2. place_design/route_design 3.2.1.3. report_timing 3.2.1.4. write_bitstream 3.2.1.5. write_sdf/write_verilog/write_vhdl 3.2.1.6. report_power 3.2.1.7. write_checkpoint 3.2.1.8. Run Complete Design Flow
3.3. FPGA Design Flow Using Tools with GUIs x
3.3.1. Project Creation 3.3.2. Design Entry 3.3.3. IP Status 3.3.4. Design Constraints 3.3.5. Synthesis 3.3.6. Design Implementation 3.3.7. Finalize Pinout 3.3.8. Viewing and Editing Design Placement 3.3.9. Static Timing Analysis 3.3.10. Generation of Device Programming Files 3.3.11. Power Analysis 3.3.12. Simulation 3.3.13. Hardware Verification 3.3.14. View Netlist 3.3.15. Design Optimization 3.3.16. Techniques to Improve Productivity 3.3.17. Cross-Probing in the Intel® Quartus® Prime Pro Edition Software
3.3.2. Design Entry x
3.3.2.1. HDL Editor 3.3.2.2. Schematic/Block Editor 3.3.2.3. State Machine Editor 3.3.2.4. IP Catalog and Parameter Editor 3.3.2.5. Platform Designer System Integration Tool 3.3.2.6. Platform Designer Component Editor
3.3.4. Design Constraints x
3.3.4.1. Assignment Editor 3.3.4.2. Create Timing Constraints with the Timing Analyzer GUI 3.3.4.3. Create Timing Constraints with the Timing Analyzer Text Editor
3.3.7. Finalize Pinout x
3.3.7.1. Pin Planner 3.3.7.2. Interface Planner
3.3.12. Simulation x
3.3.12.1. Simulation Models for Designs Containing LPMs or IP Cores
3.3.13. Hardware Verification x
3.3.13.1. System Console 3.3.13.2. Signal Tap Logic Analyzer 3.3.13.3. In-System Sources and Probes 3.3.13.4. Transceiver Toolkit 3.3.13.5. EMIF Debug Toolkit 3.3.13.6. Remote Debugging 3.3.13.7. Other Intel® FPGA Debugging Tools
3.3.14. View Netlist x
3.3.14.1. RTL Viewer 3.3.14.2. Technology Map Viewer
3.3.15. Design Optimization x
3.3.15.1. Hyper-Aware Design Flow 3.3.15.2. Physical Synthesis Optimization
3.3.16. Techniques to Improve Productivity x
3.3.16.1. Rapid Recompile 3.3.16.2. Block-Based Design Flow 3.3.16.3. Design Space Explorer II
3.4. Additional Intel® Quartus® Prime Pro Edition Features x
3.4.1. Scripting with Tcl in the Intel® Quartus® Prime Pro Edition Software
3.4.1. Scripting with Tcl in the Intel® Quartus® Prime Pro Edition Software x
3.4.1.1. Running Scripts from the DOS or UNIX Prompt 3.4.1.2. Running Scripts in Batch Mode from a Shell 3.4.1.3. Running Tcl Commands Directly from the Command Line 3.4.1.4. Running Tcl Commands Interactively from the Shell 3.4.1.5. The Intel® Quartus® Prime Tcl Console Window
4. Xilinx* to Intel® FPGA Design Conversion x
4.1. Replacing Xilinx* Primitives 4.2. Converting IP Cores 4.3. Setting Equivalent Xilinx* Design Constraints 4.4. Setting Up the Simulation Environment
4.1. Replacing Xilinx* Primitives x
4.1.1. Converting I/O Buffers 4.1.2. Changing Default I/O Standard for Pins
4.1.1. Converting I/O Buffers x
4.1.1.1. Example of Converting I/O Buffer
4.2. Converting IP Cores x
4.2.1. Converting Memory Blocks 4.2.2. Converting Mixed-Mode Clock Manager (MMCM) to Phase-Locked Loop (PLL) 4.2.3. Converting Multipliers
4.2.1. Converting Memory Blocks x
4.2.1.1. Embedded Memory Blocks 4.2.1.2. Differences Between Xilinx* Memory and Intel® FPGA Memory 4.2.1.3. Determining Memory Block and Mapping Ports 4.2.1.4. Memory Port Mapping 4.2.1.5. Example: Converting Simple Dual-Port RAM
4.2.1.2. Differences Between Xilinx* Memory and Intel® FPGA Memory x
4.2.1.2.1. Memory Mode 4.2.1.2.2. Clocking Mode 4.2.1.2.3. Write and Read Operation Triggering 4.2.1.2.4. Read-During-Write Operation at the Same Address 4.2.1.2.5. Error Correction Code (ECC) 4.2.1.2.6. Byte Enable 4.2.1.2.7. Address Clock Enable 4.2.1.2.8. Parity Bit Support 4.2.1.2.9. Memory Initialization 4.2.1.2.10. Output Synchronous Set/Reset
4.2.2. Converting Mixed-Mode Clock Manager (MMCM) to Phase-Locked Loop (PLL) x
4.2.2.1. Feature Comparison 4.2.2.2. Port Mapping Reference 4.2.2.3. Example: Converting Xilinx* MMCM into an Intel® PLL
4.2.3. Converting Multipliers x
4.2.3.1. Feature Comparison 4.2.3.2. Port Mapping 4.2.3.3. Example: Converting to the LPM_MULT IP Core 4.2.3.4. Example: Converting to the Intel® FPGA Multiply Adder IP core
4.3. Setting Equivalent Xilinx* Design Constraints x
4.3.1. Device Constraints 4.3.2. Placement Constraints 4.3.3. Timing Constraints 4.3.4. Retimer Constraints
4.3.1. Device Constraints x
4.3.1.1. DRIVE 4.3.1.2. SLEW 4.3.1.3. IOB 4.3.1.4. IOSTANDARD 4.3.1.5. KEEP
4.3.2. Placement Constraints x
4.3.2.1. PBLOCK 4.3.2.2. PACKAGE_PIN 4.3.2.3. LOC & BEL 4.3.2.4. PROHIBIT
4.3.2.1. PBLOCK x
4.3.2.1.1. Differences Between PBLOCK and Logic Lock Regions
4.3.3. Timing Constraints x
4.3.3.1. set_clock_groups
4.4. Setting Up the Simulation Environment x
4.4.1. Simulation Levels 4.4.2. HDL Support for EDA Simulators 4.4.3. Value Change Dump (VCD) Support 4.4.4. Simulating Intel FPGA IP Cores
1. Introduction to Intel® FPGA Design Flow for Xilinx* Users
2. Technology Comparison
3. FPGA Tools Comparison
4. Xilinx* to Intel® FPGA Design Conversion
5. Conclusion
6. Document Revision History for Intel® FPGA Design Flow for Xilinx* Users

2.4. Intel® FPGA Device Features

Table 2.   Intel® Arria® 10 Device Features
Performance A speed grade faster core performance and up to a 20% fMAX advantage compared to the competition, using publicly-available Intel® FPGA IP Evaluation Mode designs.
Power Intel® Arria® 10 FPGAs and SoCs are up to 40 percent lower power than previous generation FPGAs and SoCs
Industry’s only
  • Hard floating-point digital signal processing (DSP) blocks with speeds up to 1.5 tera floating-point operations per second (TFLOPS)4
  • 20 nm ARM-based SoC
Applications FPGAs and SoCs deliver the integration needed to address a wide range of applications for many industries, including communications, defense, broadcast, high-performance computing, test, and medical
Table 3.   Intel® Stratix® 10 Device Features
Performance Built on the Intel® 14 nm Tri-Gate process, Intel® Stratix® 10 devices deliver 2X core performance gains over previous-generation, high-performance FPGAs with up to 70% lower power. 5
Power Take advantage of heterogeneous 3D system-in-package (SiP) technology to integrate a monolithic FPGA core fabric with 3D SiP transceiver tiles and other advanced components in a single package.
Floating-point operations
  • The hardened floating-point operators within each DSP block, initially introduced in the Intel® Arria® 10 device family, is extended to deliver an order of magnitude greater throughput in Intel® Stratix® 10 FPGAs and SoCs.
  • Digital signal processing (DSP) designs can achieve up to 10 tera floating point operations per second (TFLOPS) of IEEE 754 single-precision floating-point operations.
Processor Highly efficient quad-core Arm* Cortex* -A53 processor cluster optimized for ultra-high performance per watt, which reduces power consumption up to 70% over previous-generation SoC FPGAs.5
Applications Uniquely positioned to address next-generation, high-performance systems in the most demanding applications including communications, datacenter acceleration, high performance computing, radar processing, ASIC prototyping, and many more.
Table 4.   Intel® Cyclone® 10 GX
Industry’s first Low-cost FPGA with IEEE 754-compliant hard floating-point DSP blocks
Applications Optimized for high-bandwidth, performance applications such as Industrial Vision, Robotics, and Automotive Infotainment.
Related Information
4 Tests measure performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase. For more complete information about performance and benchmark results, visit www.intel.com/benchmarks. Performance comparison methodology and detailed results documented in the Intel® Arria® 10 Performance Benchmarking Methodology and Results white paper on www.altera.com/arriaperformance.
5 Comparison based on Stratix® V vs. Intel® Stratix® 10 using Intel® Quartus® Prime Pro Edition 16.1 Early Beta. Stratix® V Designs were optimized using 3 step optimization process of Hyper-Retiming, Hyper-Pipelining, and Hyper-Optimization in order to utilize Intel® Stratix® 10 architecture enhancements of distributed registers in core fabric. Designs were analyzed using Quartus Prime Pro Fast Forward Compile performance exploration tool. For more details, refer to HyperFlex FPGA Architecture Overview White Paper: https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/wp/wp-01220-hyperflex-architecture-fpga-socs.pdf. Actual performance users achieve varies based on level of design optimization applied. Tests measure performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration affect actual performance. Consult other sources of information to evaluate performance as you consider a purchase. For more complete information about performance and benchmark results, visit www.intel.com/benchmark.
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