AN 307: Intel® FPGA Design Flow for Xilinx* Users

ID 683562
Date 3/20/2018
Public

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4.2.1.2.8. Parity Bit Support

Embedded memory blocks in Intel® FPGAs have built-in parity-bit support for each byte. While Xilinx* memories support separate input and output buses for parity bits, the embedded memory blocks in Intel® Stratix® 10 devices allow you to inject parity bits through the ECC encoder bypass feature.

The amount of memory in each RAM block includes the parity bits. No parity function is actually performed on the parity bits. You can use the parity bits for purposes other than ensuring data integrity; for example, to store user-specified control bits.

For more information about using the parity bit to detect memory errors, refer to the Using Parity to Detect Errors White Paper.