L-Tile and H-Tile Avalon® Memory-mapped+ Intel® FPGA IP for PCI Express* User Guide

ID 683527
Date 9/13/2024
Public
Document Table of Contents

3.2.3.9. Test Conduit

The Intel L-/H-Tile Avalon-MM+ for PCI Express IP does not export the signals in this conduit, which comes from the PCIe Hard IP.

Unused inputs must be tied low.

Table 33.  Test Conduit Signals

Signal Name

Direction

Description

test_in_i[66:0]

Input

For debugging purpose. These signals control what internal signals are brought out on the test_out_o bus.

aux_test_out_o[6:0]

Output

For debugging purpose.

test_out_o[255:0]

Output

For debugging purpose.

sim_pipe_mask_tx_pll_lock_i

Input

This signal is used only in BFM PIPE simulation.