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1. Introduction
2. Quick Start Guide
3. Block and Interface Descriptions
4. Parameters
5. Designing with the IP Core
6. Registers
7. Design Example and Testbench
8. Document Revision History for Intel® L- and H-tile Avalon® Memory-mapped+ IP for PCI Express* User Guide
A. Avalon-MM IP Variants Comparison
B. Root Port BFM
C. BFM Procedures and Functions
D. Troubleshooting and Observing the Link Status
E. Root Port Enumeration
2.1. Design Components
2.2. Directory Structure
2.3. Generating the Design Example
2.4. Simulating the Design Example
2.5. Compiling the Design Example and Programming the Device
2.6. Installing the Linux Kernel Driver
2.7. Running the Design Example Application
2.8. Ensuring the Design Example Meets Timing Requirements
6.1.1. Register Access Definitions
6.1.2. PCI Configuration Header Registers
6.1.3. PCI Express Capability Structures
6.1.4. Intel Defined VSEC Capability Header
6.1.5. Uncorrectable Internal Error Status Register
6.1.6. Uncorrectable Internal Error Mask Register
6.1.7. Correctable Internal Error Status Register
6.1.8. Correctable Internal Error Mask Register
C.1. ebfm_barwr Procedure
C.2. ebfm_barwr_imm Procedure
C.3. ebfm_barrd_wait Procedure
C.4. ebfm_barrd_nowt Procedure
C.5. ebfm_cfgwr_imm_wait Procedure
C.6. ebfm_cfgwr_imm_nowt Procedure
C.7. ebfm_cfgrd_wait Procedure
C.8. ebfm_cfgrd_nowt Procedure
C.9. BFM Configuration Procedures
C.10. BFM Shared Memory Access Procedures
C.11. BFM Log and Message Procedures
C.12. Verilog HDL Formatting Functions
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5.2. Simulation
The Quartus® Prime Pro Edition software optionally generates a functional simulation model, a testbench or design example, and vendor-specific simulator setup scripts when you generate your parameterized PCI Express* IP core. For Endpoints, the generation creates a Root Port BFM. There is no support for Root Ports in this release of the Quartus® Prime Pro Edition.
The Quartus® Prime Pro Edition supports the following simulators.
Vendor | Simulator | Version | Platform |
---|---|---|---|
Aldec | Active-HDL * | 10.3 | Windows |
Aldec | Riviera-PRO * | 2016.10 | Windows, Linux |
Cadence | Incisive Enterprise * | 15.20 | Linux |
Cadence | Xcelium* Parallel Simulator | 17.04.014 | Linux |
Mentor Graphics | ModelSim SE* | 10.5c | Windows, Linux |
Mentor Graphics | QuestaSim* | 10.5c | Windows, Linux |
Synopsys | VCS*/VCS MX* | 2016,06-SP-1 | Linux |
Note: The Intel testbench and Root Port BFM provide a simple method to do basic testing of the Application Layer logic that interfaces to the variation. This BFM allows you to create and run simple task stimuli with configurable parameters to exercise basic functionality of the example design. The testbench and Root Port BFM are not intended to be a substitute for a full verification environment. Corner cases and certain traffic profile stimuli are not covered. To ensure the best verification coverage possible, Intel recommends that you obtain commercially available PCI Express verification IP and tools, or do your own extensive hardware testing or both.