L-Tile and H-Tile Avalon® Memory-mapped+ Intel® FPGA IP for PCI Express* User Guide

ID 683527
Date 9/13/2024
Public
Document Table of Contents

3.2.1.2.2. Write Data Mover Avalon-ST Descriptor Sinks

Table 15.  Write Data Mover normal descriptor sink interface
Signal Name Direction Description
wrdm_desc_ready_o Output When asserted, this ready signal indicates the normal descriptor queue in the Write Data Mover is ready to accept data. The readyLatency is 3.
wrdm_desc_valid_i Input When asserted, this signal qualifies valid data on any cycle where data is being transferred to the normal descriptor queue. On each cycle where this signal is active, the queue samples the data.
wrdm_desc_data_i[159:0] Input

[159:152] : descriptor ID

[151:149] : application specific

[148] : reserved

[147] : single source

[146] : immediate

[145:128] : number of dwords to transfer up to 1 MB

[127:64] : destination PCIe address

[63:0] : source Avalon® -MM address / immediate data

When the single source bit is set, the source address is used for all the transfers unchanged. If the bit is not set, the address increments for each transfer

Note: When the single source bit is set, the Avalon® -MM source address and the PCIe destination address must be a multiple of 64.

When set, the immediate bit indicates immediate writes. The Write Data Mover supports immediate writes of one or two dwords. For immediate transfers, bits [31:0] or [63:0] contain the payload for one or two dwords transfers respectively. The two dwords immediate writes cannot cross a four KB boundary.

Table 16.  Write Data Mover priority descriptor sink interface
Signal Name Direction Description
wrdm_prio_ready_o Output When asserted, this ready signal indicates the priority descriptor queue in the Write Data Mover is ready to accept data. This readyLatency is 3 cycles.
wrdm_prio_valid_i Input When asserted, this signal qualifies valid data on any cycle where data is being transferred to the priority descriptor queue. On each cycle where this signal is active, the queue samples the data.
wrdm_prio_data_i[159:0] Input

[159:152] : descriptor ID

[151:149] : application specific

[148] : reserved

[147] : single source

[146] : immediate

[145:128] : number of dwords to transfer up to 1 MB

[127:64] : destination PCIe address

[63:0] : source Avalon® -MM address / immediate data

The Write Data Mover internally keeps two queues of descriptors. The priority queue has absolute priority over the normal queue. Use it carefully to avoid starving the normal queue.

If the Write Data Mover receives a descriptor on the priority interface while processing a descriptor from the normal queue, it switches to processing descriptors from the priority queue after it has completed processing the current descriptor from the normal queue. The Write Data Mover resumes processing descriptors from the normal queue once the priority queue is empty. Do not use the same descriptor ID simultaneously in the two queues as there would be no way to distinguish them on the Status Avalon-ST source interface.