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1. Introduction
2. Quick Start Guide
3. Block and Interface Descriptions
4. Parameters
5. Designing with the IP Core
6. Registers
7. Design Example and Testbench
8. Document Revision History for Intel® L- and H-tile Avalon® Memory-mapped+ IP for PCI Express* User Guide
A. Avalon-MM IP Variants Comparison
B. Root Port BFM
C. BFM Procedures and Functions
D. Troubleshooting and Observing the Link Status
E. Root Port Enumeration
2.1. Design Components
2.2. Directory Structure
2.3. Generating the Design Example
2.4. Simulating the Design Example
2.5. Compiling the Design Example and Programming the Device
2.6. Installing the Linux Kernel Driver
2.7. Running the Design Example Application
2.8. Ensuring the Design Example Meets Timing Requirements
6.1.1. Register Access Definitions
6.1.2. PCI Configuration Header Registers
6.1.3. PCI Express Capability Structures
6.1.4. Intel Defined VSEC Capability Header
6.1.5. Uncorrectable Internal Error Status Register
6.1.6. Uncorrectable Internal Error Mask Register
6.1.7. Correctable Internal Error Status Register
6.1.8. Correctable Internal Error Mask Register
C.1. ebfm_barwr Procedure
C.2. ebfm_barwr_imm Procedure
C.3. ebfm_barrd_wait Procedure
C.4. ebfm_barrd_nowt Procedure
C.5. ebfm_cfgwr_imm_wait Procedure
C.6. ebfm_cfgwr_imm_nowt Procedure
C.7. ebfm_cfgrd_wait Procedure
C.8. ebfm_cfgrd_nowt Procedure
C.9. BFM Configuration Procedures
C.10. BFM Shared Memory Access Procedures
C.11. BFM Log and Message Procedures
C.12. Verilog HDL Formatting Functions
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3.2.1. Avalon-MM Interface Summary
Avalon-MM Type | Data Bus Width | Max Burst Size | Byte Enable Granularity | Max Outstanding Read Request |
---|---|---|---|---|
Bursting Slave | 512 bits | 8 cycles | byte | 64 |
Bursting Master | 512 bits | 8 cycles | byte | 32 |
Read Data Mover Write Master | 512 bits | 8 cycles | dword | N/A |
Write Data Mover Read Master | 512 bits | 8 cycles | dword | 128 |
Config Slave | 32 bits | 1 cycle | byte | 1 |
Note: The number of read requests issued by the Write Data Mover's Avalon® -MM Read Master is controlled by the assertion of waitrequest by the connected slave(s). The Read Master can handle 128 outstanding cycles of data. You cannot set this parameter in Platform Designer. The slave needs to correctly back-pressure the master once it cannot handle the incoming requests.
Note: The 512-bit Bursting Slave interface does not support transactions where all byte enables are set to 0.