Visible to Intel only — GUID: puz1520633268245
Ixiasoft
Visible to Intel only — GUID: puz1520633268245
Ixiasoft
1.6. Transceiver Tiles
Tile | Device Type | Channel Capability | Channel Hard IP Access | |
---|---|---|---|---|
Chip-to-Chip | Backplane | |||
L-Tile | GX/SX | 26 Gbps (NRZ) | 12.5 Gbps (NRZ) | PCIe Gen3x16 |
H-Tile | GX/SX/MX/TX | 28.3 Gbps (NRZ) | 28.3 Gbps (NRZ) | PCIe Gen3x16 |
L-Tile and H-Tile
Both L and H transceiver tiles contain four transceiver banks-with a total of 24 duplex channels, eight ATX PLLs, eight fPLLs, eight CMU PLLs, a PCIe Hard IP block, and associated input reference and transmitter clock networks. L and H transceiver tiles also include 10GBASE-KR/40GBASE-KR4 FEC block in each channel.
L-Tiles have transceiver channels that support up to 26 Gbps chip-to-chip or 12.5 Gbps backplane applications. H-Tiles have transceiver channels to support 28.3 Gbps applications. H-Tile channels support fast lock-time for Gigabit-capable passive optical network (GPON).
Only Stratix® 10 GX/SX devices support L-Tiles, while most of the product line supports H-Tiles. Package migration is available with Stratix® 10 GX/SX from L-Tile to H-Tile variants.