L-Tile and H-Tile Avalon® Memory-mapped+ Intel® FPGA IP for PCI Express* User Guide

ID 683527
Date 9/13/2024
Public
Document Table of Contents

7.1.1.2. Traffic Generator and Checker (BAS Example Design Only)

This module creates read and write transactions to exercise the Bursting Slave module. You program it by writing to its control registers through its Control and Status Avalon® -MM slave interface.

The traffic that it generates and expects is a sequence of incrementing dwords.

In the checking process, the first dword is accepted as-is, and the following dwords are checked to be incrementing.