L-Tile and H-Tile Avalon® Memory-mapped+ Intel® FPGA IP for PCI Express* User Guide

ID 683527
Date 9/13/2024
Public
Document Table of Contents

3.2.1.1.2. Read Data Mover Avalon-ST Descriptor Sinks

The Read Data Mover has two Avalon® -ST sinks through which it receives the descriptors that define the data transfers. One of the interfaces receives descriptors for normal data transfers, while the other receives descriptors for high-priority data transfers.
Table 11.  Read Data Mover normal descriptor sink interface
Signal Name Direction Description
rddm_desc_ready_o Output When asserted, this ready signal indicates the normal descriptor queue in the Read Data Mover is ready to accept data. The ready latency of this interface is 3 cycles.
rddm_desc_valid_i Input When asserted, this signal qualifies valid data on any cycle where data is being transferred to the normal descriptor queue. On each cycle where this signal is active, the queue samples the data.
rddm_desc_data_i[159:0] Input

[159:152] : descriptor ID

[151:149] : application specific

[148] : single destination

[147] : reserved

[146] : reserved

[145:128] : number of dwords to transfer up to 1 MB

[127:64] : destination Avalon® -MM address

[63:0] : source PCIe address

When the single destination bit is set, the transfers use the same destination address. If the bit is not set, the address increments for each transfer.

Note: When the single source bit is set, the Avalon® -MM destination address and the PCIe* source address must be a multiple of 64.
Table 12.  Read Data Mover priority descriptor sink interface
Signal Name Direction Description
rddm_prio_ready_o Output When asserted, this ready signal indicates the priority descriptor queue in the Read Data Mover is ready to accept data.This ready latency of this interface is 3 cycles.
rddm_prio_valid_i Input When asserted, this signal qualifies valid data on any cycle where data is being transferred to the priority descriptor queue. On each cycle where this signal is active, the queue samples the data.
rddm_prio_data_i[159:0] Input

[159:152] : descriptor ID

[151:149] : application specific

[148] : single destination

[147] : reserved

[146] : reserved

[145:128] : number of dwords to transfer up to 1 MB

[127:64] : destination Avalon® -MM address

[63:0] : source PCIe address

The Read Data Mover internally keeps two queues of descriptors. The priority queue has absolute priority over the normal queue. Use it carefully to avoid starving the normal queue.

If the Read Data Mover receives a descriptor on the priority interface while processing a descriptor from the normal queue, it switches to processing descriptors from the priority queue as soon as it has completed the current descriptor. The Read Data Mover resumes processing the descriptors from the normal queue once the priority queue is empty. Do not use the same descriptor ID simultaneously in the two queues as there would be no way to distinguish them on the Status Avalon-ST source interface.