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1. Introduction
2. Quick Start Guide
3. Block and Interface Descriptions
4. Parameters
5. Designing with the IP Core
6. Registers
7. Design Example and Testbench
8. Document Revision History for Intel® L- and H-tile Avalon® Memory-mapped+ IP for PCI Express* User Guide
A. Avalon-MM IP Variants Comparison
B. Root Port BFM
C. BFM Procedures and Functions
D. Troubleshooting and Observing the Link Status
E. Root Port Enumeration
2.1. Design Components
2.2. Directory Structure
2.3. Generating the Design Example
2.4. Simulating the Design Example
2.5. Compiling the Design Example and Programming the Device
2.6. Installing the Linux Kernel Driver
2.7. Running the Design Example Application
2.8. Ensuring the Design Example Meets Timing Requirements
6.1.1. Register Access Definitions
6.1.2. PCI Configuration Header Registers
6.1.3. PCI Express Capability Structures
6.1.4. Intel Defined VSEC Capability Header
6.1.5. Uncorrectable Internal Error Status Register
6.1.6. Uncorrectable Internal Error Mask Register
6.1.7. Correctable Internal Error Status Register
6.1.8. Correctable Internal Error Mask Register
C.1. ebfm_barwr Procedure
C.2. ebfm_barwr_imm Procedure
C.3. ebfm_barrd_wait Procedure
C.4. ebfm_barrd_nowt Procedure
C.5. ebfm_cfgwr_imm_wait Procedure
C.6. ebfm_cfgwr_imm_nowt Procedure
C.7. ebfm_cfgrd_wait Procedure
C.8. ebfm_cfgrd_nowt Procedure
C.9. BFM Configuration Procedures
C.10. BFM Shared Memory Access Procedures
C.11. BFM Log and Message Procedures
C.12. Verilog HDL Formatting Functions
Visible to Intel only — GUID: iaq1523061723583
Ixiasoft
A. Avalon-MM IP Variants Comparison
Features | Intel L-/H-Tile Avalon-MM for PCI Express IP | Intel L-/H-Tile Avalon-MM+ for PCI Express IP | Comments |
---|---|---|---|
PCIe Link Widths | x1/x2/x4/x8 | x16 | |
Lane Rates | 2.5/5/8 Gb/s | 8 Gb/s Lane Rate | |
Root Port Support | Supported | N/A | |
Endpoint Support | Supported | Supported | |
Data Bus Width on Avalon-MM Interface (Non-Bursting) | 32-bit | N/A | |
Data Bus Width on Avalon-MM Interface (Bursting) | 256-bit | 512-bit | |
Application Layer clock | 250 MHz | 250 MHz | |
Maximum Payload Size (MPS) | 128/256/512 Bytes | 128/256/512 Bytes | Default value is 512 |
Maximum Read Request Size (MRRS) | 128/256/512 Bytes | 128/256/512 Bytes | Default value is 512 |
Maximum Outstanding Read Requests (Non-Bursting) | 1 | N/A | |
Maximum Outstanding Read Requests (Bursting) | 32 | 64 | |
Maximum Burst Size (Non-Bursting) | 1 cycle | N/A | |
Maximum Burst Size (Bursting) | 16 cycles | 8 cycles | |
Byte Enable Granularity (Non-Bursting) | Byte | N/A | |
Byte Enable Granularity HPRXM (Bursting) | Byte | Byte | For single-cycle reads, byte granularity is supported. For multiple-cycle reads, all byte enables are active. |
Byte Enable Granularity HPTXS (Bursting) | Dword | Byte | |
Write Data Mover | WR_DMA interface | WRDM interface | |
Number of Descriptor Queues for Write Data Mover | One | Two | The Intel L-/H-Tile Avalon-MM+ for PCI Express IP has a normal descriptor queue and a priority descriptor queue |
Single Source Address Mode for Write Data Mover | N/A | Supported | Platform Designer Interconnect may increment the address for the Intel L-/H-Tile Avalon-MM+ for PCI Express IP |
Read Data Mover | RD_DMA interface | RDDM interface | |
Number of Descriptor Queues for Read Data Mover | One | Two | The Intel L-/H-Tile Avalon-MM+ for PCI Express IP has a normal descriptor queue and a priority descriptor queue |
Single Destination Address Mode for Read Data Mover | N/A | Supported | Platform Designer Interconnect may increment the address for the Intel L-/H-Tile Avalon-MM+ for PCI Express IP |
Avalon-MM Slave | TXS interface | N/A | |
Avalon-MM Master | RXM Interface | N/A | |
High-Performance Avalon-MM Slave | HPTXS interface | BAS (Bursting Avalon-MM Slave) interface | |
High-Performance Avalon-MM Master | HPRXM interface | BAM (Bursting Avalon-MM Master) interface | |
Simultaneous support for DMA modules and Avalon-MM masters and slaves | Yes | Yes | |
Multi-function Support | N/A | N/A | |
CRA (Configuration Register Access) | CRA (Configuration Register Access) | N/A | |
CEB (Configuration Extension Bus) | CEB (Configuration Extension Bus) | N/A | |
MSI, MSI-X | MSI, MSI-X Interfaces | Not available as separate interfaces. Can be accessed via tl_cfg interface. | Because MSI and MSI-X conduits are not exported by this IP core, the address and data information necessary to send an MSI or MSI-X can be extracted from the tl_cfg interface. Alternatively, that information can be extracted from an immediate write descriptor if you enable that feature by setting bit [146] in the descriptor. |
External DMA Controller | Supported | Supported | User has to provide the external DMA controller. The design example contains a DMA controller as an example. |
Internal DMA Controller | Supported | N/A | |
Number of RX Masters | Up to 6 (one for each BAR) | Single Bursting Master with BAR sideband signals. Supports up to 7 BARs (including expansion ROM BAR) | Multiple BARs are supported by having BAR ID included in a conduit extension of the BAM address |
TPH (TLP Processing Hint) | N/A | N/A | |
ATS (Address Translation Service) | N/A | N/A | |
Error Handling | N/A | N/A | |
AER (Advanced Error Reporting) | Supported (always enabled) | Supported (always enabled) | |
Hard IP Reconfiguration | HIP_RECONFIG interface | HIP_RECONFIG interface | |
XCVR Reconfiguration | XCVR_RECONFIG interface | XCVR_RECONFIG interface | |
FPLL Reconfiguration | RECONFIG_PLL0 interface | RECONFIG_PLL0 interface | |
LC PLL Reconfiguration | RECONFIG_PLL1 interface | RECONFIG_PLL1 interface | |
Support for PCIe Link Inspector | Supported | N/A | It is supported up to Gen3x8 for both Avalon® -ST and Avalon® -MM. It is not yet supported in Gen3x16. |
Design Example Availability | Yes | Yes | |
Software Programming Model | Single descriptor queue in Data Movers, so no prioritization of simultaneous DMA transactions. | Better prioritization of simultaneous DMA transactions due to the different descriptor queues. Improved interrupt generation. |