L-Tile and H-Tile Avalon® Memory-mapped+ Intel® FPGA IP for PCI Express* User Guide

ID 683527
Date 9/13/2024
Public
Document Table of Contents

A. Avalon-MM IP Variants Comparison

Table 65.  Differences Between the Intel L-/H-Tile Avalon-MM for PCI Express IP and Intel L-/H-Tile Avalon-MM+ for PCI Express IP
Features Intel L-/H-Tile Avalon-MM for PCI Express IP Intel L-/H-Tile Avalon-MM+ for PCI Express IP Comments
PCIe Link Widths x1/x2/x4/x8 x16
Lane Rates 2.5/5/8 Gb/s 8 Gb/s Lane Rate
Root Port Support Supported N/A
Endpoint Support Supported Supported
Data Bus Width on Avalon-MM Interface (Non-Bursting) 32-bit N/A
Data Bus Width on Avalon-MM Interface (Bursting) 256-bit 512-bit
Application Layer clock 250 MHz 250 MHz
Maximum Payload Size (MPS) 128/256/512 Bytes 128/256/512 Bytes Default value is 512
Maximum Read Request Size (MRRS) 128/256/512 Bytes 128/256/512 Bytes Default value is 512
Maximum Outstanding Read Requests (Non-Bursting) 1 N/A
Maximum Outstanding Read Requests (Bursting) 32 64
Maximum Burst Size (Non-Bursting) 1 cycle N/A
Maximum Burst Size (Bursting) 16 cycles 8 cycles
Byte Enable Granularity (Non-Bursting) Byte N/A
Byte Enable Granularity HPRXM (Bursting) Byte Byte For single-cycle reads, byte granularity is supported. For multiple-cycle reads, all byte enables are active.
Byte Enable Granularity HPTXS (Bursting) Dword Byte
Write Data Mover WR_DMA interface WRDM interface
Number of Descriptor Queues for Write Data Mover One Two The Intel L-/H-Tile Avalon-MM+ for PCI Express IP has a normal descriptor queue and a priority descriptor queue
Single Source Address Mode for Write Data Mover N/A Supported Platform Designer Interconnect may increment the address for the Intel L-/H-Tile Avalon-MM+ for PCI Express IP
Read Data Mover RD_DMA interface RDDM interface
Number of Descriptor Queues for Read Data Mover One Two The Intel L-/H-Tile Avalon-MM+ for PCI Express IP has a normal descriptor queue and a priority descriptor queue
Single Destination Address Mode for Read Data Mover N/A Supported Platform Designer Interconnect may increment the address for the Intel L-/H-Tile Avalon-MM+ for PCI Express IP
Avalon-MM Slave TXS interface N/A
Avalon-MM Master RXM Interface N/A
High-Performance Avalon-MM Slave HPTXS interface BAS (Bursting Avalon-MM Slave) interface
High-Performance Avalon-MM Master HPRXM interface BAM (Bursting Avalon-MM Master) interface
Simultaneous support for DMA modules and Avalon-MM masters and slaves Yes Yes
Multi-function Support N/A N/A
CRA (Configuration Register Access) CRA (Configuration Register Access) N/A
CEB (Configuration Extension Bus) CEB (Configuration Extension Bus) N/A
MSI, MSI-X MSI, MSI-X Interfaces Not available as separate interfaces. Can be accessed via tl_cfg interface. Because MSI and MSI-X conduits are not exported by this IP core, the address and data information necessary to send an MSI or MSI-X can be extracted from the tl_cfg interface. Alternatively, that information can be extracted from an immediate write descriptor if you enable that feature by setting bit [146] in the descriptor.
External DMA Controller Supported Supported User has to provide the external DMA controller. The design example contains a DMA controller as an example.
Internal DMA Controller Supported N/A
Number of RX Masters Up to 6 (one for each BAR) Single Bursting Master with BAR sideband signals. Supports up to 7 BARs (including expansion ROM BAR) Multiple BARs are supported by having BAR ID included in a conduit extension of the BAM address
TPH (TLP Processing Hint) N/A N/A
ATS (Address Translation Service) N/A N/A
Error Handling N/A N/A
AER (Advanced Error Reporting) Supported (always enabled) Supported (always enabled)
Hard IP Reconfiguration HIP_RECONFIG interface HIP_RECONFIG interface
XCVR Reconfiguration XCVR_RECONFIG interface XCVR_RECONFIG interface
FPLL Reconfiguration RECONFIG_PLL0 interface RECONFIG_PLL0 interface
LC PLL Reconfiguration RECONFIG_PLL1 interface RECONFIG_PLL1 interface
Support for PCIe Link Inspector Supported N/A It is supported up to Gen3x8 for both Avalon® -ST and Avalon® -MM. It is not yet supported in Gen3x16.
Design Example Availability Yes Yes
Software Programming Model Single descriptor queue in Data Movers, so no prioritization of simultaneous DMA transactions. Better prioritization of simultaneous DMA transactions due to the different descriptor queues. Improved interrupt generation.