Visible to Intel only — GUID: yww1520633367535
Ixiasoft
Visible to Intel only — GUID: yww1520633367535
Ixiasoft
C.11.2. ebfm_log_stop_sim Verilog HDL Function
The ebfm_log_stop_sim procedure stops the simulation.
Location |
altrpcietb_g3bfm_log.v |
|
---|---|---|
Syntax |
Verilog HDL: return:=ebfm_log_stop_sim(success); |
|
Argument |
success | When set to a 1, this process stops the simulation with a message indicating successful completion. The message is prefixed with SUCCESS. Otherwise, this process stops the simulation with a message indicating unsuccessful completion. The message is prefixed with FAILURE. |
Return |
Always 0 |
This value applies only to the Verilog HDL function. |