Visible to Intel only — GUID: uoj1597428539513
Ixiasoft
Visible to Intel only — GUID: uoj1597428539513
Ixiasoft
3.2.3.4. Configuration Output Interface
Signal | Direction | Description |
---|---|---|
tl_cfg_add[3:0] (H-tile) tl_cfg_add[4:0] (L-tile) |
Output | Address of the TLP register. This signal is an index indicating which Configuration Space register information is being driven onto tl_cfg_ctl[31:0]. |
tl_cfg_ctl[31:0] | Output | The tl_cfg_ctl signal is multiplexed and contains a subset of contents of the Configuration Space registers. |
tl_cfg_func[1:0] | Output | Specifies the function whose Configuration Space register values are being driven onto tl_cfg_ctl. The following encodings are defined:
|
Information on the tl_cfg_ctl bus is time-division multiplexed (TDM). Examples of information multiplexed onto the tl_cfg_ctl bus include device number, bus number, MSI information (address, data, mask) and AER information. For more details, refer to the Transaction Layer Configuration Space Interface section of the Stratix® 10 Avalon® streaming and Single Root I/O Virtualization (SR-IOV) Interface for PCI Express Solutions User Guide.