2022.09.20 |
22.1 |
20.0.1 |
Updated the outclk2 and outclk4 phase shift values in the topic listing the IOPLL parameter values for external PLL mode. |
2022.03.28 |
22.1 |
20.0.1 |
- Updated a topic about timing analysis:
- Retitled the topic from Timing Analysis for the External PLL Mode to Timing Analysis when Using PLL Core Clocks.
- Updated the content to clarify that you must specify the derive_pll_clocks command in your .sdc file if you use PLL core clocks regardless if you use internal or external PLLs.
- Updated the rx_dpa_hold signal description.
- Updated the user guide archives section. For the latest and previous versions of this user guide, refer to the LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices.
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2021.07.13 |
21.2 |
20.0.0 |
Updated the information about the receiver timing analysis in non-DPA mode. |
2021.05.28 |
21.1 |
20.0.0 |
- Updated the code to add to the .sdc file to specify the RCCS value.
- Added the RCCS (ps) parameter to the LVDS SERDES IP.
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2020.03.29 |
21.1 |
20.0.0 |
Updated the LVDS SERDES IP version number. |
2020.09.25 |
20.2 |
19.4.0 |
Removed the Use clock-pin drive parameter from the LVDS SERDES IP core general settings. |
2020.07.10 |
20.2 |
19.4.0 |
- Added link to the KDB article about missing RSKM report in Intel® Quartus® Prime Pro Edition in the section about I/O timing analysis.
- Updated the footnote in the Comparison of LVDS SERDES IP Core with Stratix® V SERDES topic to clarify that the operation frequency range depends on the product line, speed grade, and SERDES factor.
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2020.05.06 |
19.4 |
19.3.0 |
Added the Tcl error: ERROR: Argument <clk_object> is a collection with more than one object. Specify a collection with one object. while executing "get_clock_info -period [get_clocks [lindex $fclk_setting_name 0]] KDB link in the Timing Analysis for the External PLL Mode topic. |
2020.03.10 |
19.4 |
19.3.0 |
- Added Release Information topic.
- Updated the Timing Analysis for the External PLL Mode topic with a command to include in the .sdc file to derive all PLL clocks.
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2019.05.03 |
19.1 |
19.1 |
- Moved the Usage Modes Summary of the LVDS SERDES table to the following documents:
- Updated the table that lists the functional modes of the LVDS SERDES IP core to specify that all functional modes support SERDES factors of 3 to 10.
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2019.01.30 |
18.1 |
18.1 |
Added Usage Modes Summary of the LVDS SERDES table in LVDS IP Core Features topic. |
2018.12.05 |
18.1 |
18.1 |
- Updated the topic about the timing analysis for the external PLL mode to improve clarity.
- Updated the topic about the simulation design example to add a note about the non-synthesizable simulation driver.
- Renamed "TimeQuest Timing Analyzer" to "Timing Analyzer".
- Renamed "SignalTap" to "Signal Tap".
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2018.09.06 |
18.0 |
18.0 |
- Removed ext_loaden signal in figures showing the LVDS receiver in soft-CDR mode.
- Specified that connecting the IOPLL loaden signal to the LVDS receiver ext_loaden signal is not required for LVDS receivers in soft-CDR mode.
- Updated the figures descriptions in the guideline topic about using LVDS transmitters and receivers in the same I/O bank to clarify that the figures show connections that you need to make.
- Updated the synthesizable design example topic to improve clarity.
- Updated the names of the following IP cores:
- Intel FPGA LVDS SERDES to LVDS SERDES Intel FPGA IP
- Intel FPGA IOPLL to IOPLL Intel FPGA IP
- Updated the document title.
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