LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
Visible to Intel only — GUID: sam1412833550289
Ixiasoft
Visible to Intel only — GUID: sam1412833550289
Ixiasoft
LVDS SERDES IP Core Functional Description
Each LVDS SERDES IP core channel contains a SERDES, a bitslip block, DPA circuitry for all modes, a high-speed clock tree (LVDS clock tree) and forwarded clock signal for soft-CDR mode. Therefore, an n-channel LVDS interface contains n-serdes_dpa blocks.
The I/O PLLs drive the LVDS clock tree, providing clocking signals to the LVDS SERDES IP core channel in the I/O bank.
Path | Block | Mode | Clock Domain |
---|---|---|---|
TX Data Path | Serializer | TX | LVDS |
RX Data Path | DPA |
|
DPA |
DPA FIFO | DPA-FIFO | LVDS–DPA domain crossing | |
|
|
LVDS | |
Soft CDR | DPA | ||
Clock Generation and Multiplexers | Local Clock Generator | Soft-CDR | Generates PCLK and load_enable in these modes |
SERDES Clock Multiplexers | All | Selects LVDS clock sources for all modes |