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Release Information
LVDS SERDES Intel® FPGA IP Features
LVDS SERDES IP Core Functional Modes
LVDS SERDES IP Core Functional Description
LVDS SERDES IP Initialization and Reset
LVDS SERDES Intel® FPGA IP Signals
LVDS SERDES Intel® FPGA IP Parameter Settings
LVDS SERDES Intel® FPGA IP Timing
LVDS SERDES Intel® FPGA IP Design Examples
Additional LVDS SERDES IP Core References
LVDS SERDES Intel® FPGA IP User Guide Archives
Document Revision History for LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
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Migrating Your ALTLVDS_TX and ALTLVDS_RX IP Cores
To migrate your ALTLVDS_TX and ALTLVDS_RX IP cores to the LVDS SERDES Intel® FPGA IP, follow these steps:
- Open your ALTLVDS_TX or ALTLVDS_RX core in the IP parameter editor.
- In the Currently selected device family, select Arria 10 or Cyclone 10 GX.
- Click Finish to open the LVDS SERDES IP core parameter editor. The parameter editor configures the LVDS SERDES IP core settings similar to the ALTLVDS_TX or ALTLVDS_RX IP core settings.
- If there are any incompatible settings between the two IP cores, select new supported settings.
- Click Finish to regenerate the IP core.
- Replace your ALTLVDS_TX or ALTLVDS_RX IP core instantiation in RTL with the LVDS SERDES IP core.
Note: The LVDS SERDES IP core port names may not match the ALTLVDS_TX or ALTLVDS_RX IP core port names. Therefore, simply changing the IP core name in the instantiation may not be sufficient.