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Release Information
LVDS SERDES Intel® FPGA IP Features
LVDS SERDES IP Core Functional Modes
LVDS SERDES IP Core Functional Description
LVDS SERDES IP Initialization and Reset
LVDS SERDES Intel® FPGA IP Signals
LVDS SERDES Intel® FPGA IP Parameter Settings
LVDS SERDES Intel® FPGA IP Timing
LVDS SERDES Intel® FPGA IP Design Examples
Additional LVDS SERDES IP Core References
LVDS SERDES Intel® FPGA IP User Guide Archives
Document Revision History for LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
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Aligning Word Boundaries
After initializing the LVDS SERDES IP in DPA or non-DPA mode, perform these steps to align the word boundaries.
- Assert the rx_bitslip_reset port for at least one parallel clock cycle, and then deassert the rx_bitslip_reset port.
- Begin word alignment by applying pulses as required to the rx_bitslip_ctrl port.
After the word boundaries are established on each channel, the interface is ready for operation.