LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

Download PDF
ID 683520
Date 9/20/2022
Public
Document Table of Contents
Document Table of Contents x
LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices x
Release Information LVDS SERDES Intel® FPGA IP Features LVDS SERDES IP Core Functional Modes LVDS SERDES IP Core Functional Description LVDS SERDES IP Initialization and Reset LVDS SERDES Intel® FPGA IP Signals LVDS SERDES Intel® FPGA IP Parameter Settings LVDS SERDES Intel® FPGA IP Timing LVDS SERDES Intel® FPGA IP Design Examples Additional LVDS SERDES IP Core References LVDS SERDES Intel® FPGA IP User Guide Archives Document Revision History for LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
LVDS SERDES IP Core Functional Description x
Serializer DPA FIFO Bitslip Deserializer
LVDS SERDES IP Initialization and Reset x
Initializing the LVDS SERDES IP in Non-DPA Mode Initializing the LVDS SERDES IP in DPA Mode Resetting the DPA Word Boundaries Alignment
Word Boundaries Alignment x
Aligning Word Boundaries
LVDS SERDES Intel® FPGA IP Parameter Settings x
LVDS SERDES Intel® FPGA IP General Settings LVDS SERDES Intel® FPGA IP PLL Settings LVDS SERDES Intel® FPGA IP Receiver Settings LVDS SERDES Intel® FPGA IP Transmitter Settings LVDS SERDES IP Core Clock Resource Summary
LVDS SERDES Intel® FPGA IP Receiver Settings x
Receiver Input Clock Parameters Setup
LVDS SERDES Intel® FPGA IP Transmitter Settings x
Setting the Transmitter Output Clock Parameters
LVDS SERDES Intel® FPGA IP Timing x
I/O Timing Analysis FPGA Timing Analysis Timing Analysis when Using PLL Core Clocks Timing Closure Guidelines for Internal FPGA Paths
I/O Timing Analysis x
Obtaining RSKM Report Obtaining TCCS Report
LVDS SERDES Intel® FPGA IP Design Examples x
LVDS SERDES IP Synthesizable Intel® Quartus® Prime Design Examples LVDS SERDES IP Simulation Design Example Combined LVDS SERDES IP Transmitter and Receiver Design Example LVDS SERDES IP Dynamic Phase Shift Design Example
Additional LVDS SERDES IP Core References x
IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices LVDS Interface with External PLL Mode LVDS Transmitters and Receivers in the Same I/O Bank Comparison of LVDS SERDES IP Core with Stratix® V SERDES
IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices x
Migrating Your ALTLVDS_TX and ALTLVDS_RX IP Cores
LVDS Interface with External PLL Mode x
IOPLL IP Signal Interface with LVDS SERDES IP IOPLL Parameter Values for External PLL Mode Connection between IOPLL IP and LVDS SERDES IP in External PLL Mode
LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

Document Revision History for LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

Document Version Intel® Quartus® Prime Version IP Version Changes
2022.09.20 22.1 20.0.1 Updated the outclk2 and outclk4 phase shift values in the topic listing the IOPLL parameter values for external PLL mode.
2022.03.28 22.1 20.0.1
  • Updated a topic about timing analysis:
    • Retitled the topic from Timing Analysis for the External PLL Mode to Timing Analysis when Using PLL Core Clocks.
    • Updated the content to clarify that you must specify the derive_pll_clocks command in your .sdc file if you use PLL core clocks regardless if you use internal or external PLLs.
  • Updated the rx_dpa_hold signal description.
  • Updated the user guide archives section. For the latest and previous versions of this user guide, refer to the LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices.
2021.07.13 21.2 20.0.0 Updated the information about the receiver timing analysis in non-DPA mode.
2021.05.28 21.1 20.0.0
  • Updated the code to add to the .sdc file to specify the RCCS value.
  • Added the RCCS (ps) parameter to the LVDS SERDES IP.
2020.03.29 21.1 20.0.0 Updated the LVDS SERDES IP version number.
2020.09.25 20.2 19.4.0 Removed the Use clock-pin drive parameter from the LVDS SERDES IP core general settings.
2020.07.10 20.2 19.4.0
  • Added link to the KDB article about missing RSKM report in Intel® Quartus® Prime Pro Edition in the section about I/O timing analysis.
  • Updated the footnote in the Comparison of LVDS SERDES IP Core with Stratix® V SERDES topic to clarify that the operation frequency range depends on the product line, speed grade, and SERDES factor.
2020.05.06 19.4 19.3.0 Added the Tcl error: ERROR: Argument <clk_object> is a collection with more than one object. Specify a collection with one object. while executing "get_clock_info -period [get_clocks [lindex $fclk_setting_name 0]] KDB link in the Timing Analysis for the External PLL Mode topic.
2020.03.10 19.4 19.3.0
  • Added Release Information topic.
  • Updated the Timing Analysis for the External PLL Mode topic with a command to include in the .sdc file to derive all PLL clocks.
2019.05.03 19.1 19.1
2019.01.30 18.1 18.1 Added Usage Modes Summary of the LVDS SERDES table in LVDS IP Core Features topic.
2018.12.05 18.1 18.1
  • Updated the topic about the timing analysis for the external PLL mode to improve clarity.
  • Updated the topic about the simulation design example to add a note about the non-synthesizable simulation driver.
  • Renamed "TimeQuest Timing Analyzer" to "Timing Analyzer".
  • Renamed "SignalTap" to "Signal Tap".
2018.09.06 18.0 18.0
  • Removed ext_loaden signal in figures showing the LVDS receiver in soft-CDR mode.
  • Specified that connecting the IOPLL loaden signal to the LVDS receiver ext_loaden signal is not required for LVDS receivers in soft-CDR mode.
  • Updated the figures descriptions in the guideline topic about using LVDS transmitters and receivers in the same I/O bank to clarify that the figures show connections that you need to make.
  • Updated the synthesizable design example topic to improve clarity.
  • Updated the names of the following IP cores:
    • Intel FPGA LVDS SERDES to LVDS SERDES Intel FPGA IP
    • Intel FPGA IOPLL to IOPLL Intel FPGA IP
  • Updated the document title.
Date Version Changes
November 2017 2017.11.06
  • Corrected typographical error in the example showing the parameter values to generate output clock in external PLL mode by updating "c0" to "outclk0".
  • Added more description for the Enable tx_coreclock port parameter option to describe how configure it in external PLL mode.
  • Updated the description of the tx_coreclock signal.
  • Added Intel® Cyclone® 10 GX device support.
  • Renamed the IP core from "Altera LVDS SERDES" to "LVDS SERDES".
  • Specified that in Intel® Arria® 10 devices, the maximum operation frequency for SERDES factor 3 is 1.25 GHz.
  • Restructured the information in the topic about connecting the external PLL to the LVDS receiver and transmitter. Moved some of the information to the topic about using external PLL for combined LVDS transmitters and receivers in the same I/O bank.
May 2017 2017.05.08
  • Updated the topic about the LVDS interface with external PLL mode to clarify that the Clock Resource Summary tab in the LVDS SERDES IP core parameter editor provides the details for the signals required from the IOPLL IP core.
  • Updated the description for the Number of channels parameter in the table listing the LVDS SERDES General Settings tab to improve clarity and specify the placement of the refclk and tx_outclock pins.
  • Rebranded as Intel.
August 2016 2016.08.05
  • Updated the topics about using the LVDS interface with external PLL mode. The update adds examples and connection diagrams for using transmitter channels that span multiple banks and shared with receiver channels in DPA and soft-CDR modes.
  • Restructured the section about IP core initialization and reset to simplify and improve clarity.
December 2015 2015.12.14
  • Rewrote and restructured the document to improve clarity and for ease of reference.
  • Updated the signal names generated by the LVDS SERDES internal PLL.
  • Removed the I/O timing analysis topics and added links to the relevant topics in the Arria 10 Core Fabric and General Purpose I/Os Handbook.
  • Updated the core clock cycles to wait before checking if the data is aligned for bitslip from five cycles to four cycles.
  • Updated the number of core clock cycles the rx_bitslip_max signal is asserted after rollover from five cycles to four cycles.
  • Removed the statement about waiting two core clock cycles before resetting the bitslip after FIFO resets.
  • Updated the section about design examples. The LVDS SERDES IP core now provides more design examples.
  • Added topics about creating LVDS interfaces using external PLL in the additional references section.
  • Updated the bitslip rollover value in the topic about receiver settings. The bitslip rollover value is now set automatically to the deserialization factor.
  • Added related information links from several topics to relevant topics in the Intel® Arria® 10 device handbook and datasheet.
August, 2014 2014.08.18
  • Clarified that you must wait five core clock cycles before checking if the data is aligned for bitslip circuitry.
  • Changed the rx_out[9:0] signal to rx_out[7:0] for the deserializer.
  • Clarified that if one of the pins is taken for the refclk, then the value is 1 to 71 for TX and 1 to 23 for RX. This change is implemented for the Number of channels parameter.
  • Clarified that if one of the pins is taken for the tx_outclock, then the value is 1 to 71 for TX. This change is implemented for the Number of channels parameter.
  • Added a new parameter (Use backwards-compatible port names).
  • The Use external PLL is supported in the 14.0a10 release. The Clock Resource Summary tab guides you to configure your external PLL.
  • Removed the Enable pll_locked port and Enable rx_dpa_locked port parameters.
  • Added the external PLL signals.
  • Added timing information.
November, 2013 2013.11.29 Initial release.
Level Two Title