LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

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ID 683520
Date 9/20/2022
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Document Table of Contents x
LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices x
Release Information LVDS SERDES Intel® FPGA IP Features LVDS SERDES IP Core Functional Modes LVDS SERDES IP Core Functional Description LVDS SERDES IP Initialization and Reset LVDS SERDES Intel® FPGA IP Signals LVDS SERDES Intel® FPGA IP Parameter Settings LVDS SERDES Intel® FPGA IP Timing LVDS SERDES Intel® FPGA IP Design Examples Additional LVDS SERDES IP Core References LVDS SERDES Intel® FPGA IP User Guide Archives Document Revision History for LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
LVDS SERDES IP Core Functional Description x
Serializer DPA FIFO Bitslip Deserializer
LVDS SERDES IP Initialization and Reset x
Initializing the LVDS SERDES IP in Non-DPA Mode Initializing the LVDS SERDES IP in DPA Mode Resetting the DPA Word Boundaries Alignment
Word Boundaries Alignment x
Aligning Word Boundaries
LVDS SERDES Intel® FPGA IP Parameter Settings x
LVDS SERDES Intel® FPGA IP General Settings LVDS SERDES Intel® FPGA IP PLL Settings LVDS SERDES Intel® FPGA IP Receiver Settings LVDS SERDES Intel® FPGA IP Transmitter Settings LVDS SERDES IP Core Clock Resource Summary
LVDS SERDES Intel® FPGA IP Receiver Settings x
Receiver Input Clock Parameters Setup
LVDS SERDES Intel® FPGA IP Transmitter Settings x
Setting the Transmitter Output Clock Parameters
LVDS SERDES Intel® FPGA IP Timing x
I/O Timing Analysis FPGA Timing Analysis Timing Analysis when Using PLL Core Clocks Timing Closure Guidelines for Internal FPGA Paths
I/O Timing Analysis x
Obtaining RSKM Report Obtaining TCCS Report
LVDS SERDES Intel® FPGA IP Design Examples x
LVDS SERDES IP Synthesizable Intel® Quartus® Prime Design Examples LVDS SERDES IP Simulation Design Example Combined LVDS SERDES IP Transmitter and Receiver Design Example LVDS SERDES IP Dynamic Phase Shift Design Example
Additional LVDS SERDES IP Core References x
IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices LVDS Interface with External PLL Mode LVDS Transmitters and Receivers in the Same I/O Bank Comparison of LVDS SERDES IP Core with Stratix® V SERDES
IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices x
Migrating Your ALTLVDS_TX and ALTLVDS_RX IP Cores
LVDS Interface with External PLL Mode x
IOPLL IP Signal Interface with LVDS SERDES IP IOPLL Parameter Values for External PLL Mode Connection between IOPLL IP and LVDS SERDES IP in External PLL Mode
LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

LVDS SERDES Intel® FPGA IP Signals

Table 6.  Common LVDS SERDES IP TX and RX Signals
Signal Name Width Direction Type Description
inclock 1 Input Clock

PLL reference clock.
pll_areset 1 Input Reset

Active-high asynchronous reset to all blocks in LVDS SERDES IP and PLL.

pll_locked 1 Output Control

Asserts when internal PLL locks.
Table 7.   LVDS SERDES IP Core RX SignalsIn this table, N represents the LVDS interface width and the number of serial channels while J represents the SERDES factor of the interface.
Signal Name Width Direction Type Description

rx_in

N Input Data

LVDS serial input data.
rx_bitslip_reset N Input Reset Asynchronous, active-high reset to the clock-data alignment circuitry (bit slip).
rx_bitslip_ctrl N Input Control
  • Positive-edge triggered increment for bit slip circuitry.
  • Each assertion adds one bit of latency to the received bit stream.
rx_dpa_hold N Input Control
  • Asynchronous, active-high signal that prevents the DPA circuitry from switching to a new clock phase on the target channel.
    • Held high—selected channels hold their current phase setting.
    • Held low—the DPA block on selected channels monitors the phase of the incoming data stream continuously and selects a new clock phase when needed.
  • Applicable in DPA-FIFO mode only.
rx_dpa_reset N Input Reset
  • Asynchronous, active-high reset to DPA blocks.
  • Minimum pulse width: one parallel clock period.
  • Applicable in DPA-FIFO and soft-CDR modes only.
rx_fifo_reset N Input Reset
  • Asynchronous, active-high reset to FIFO block.
  • Minimum pulse width: one parallel clock period.
  • Applicable in DPA-FIFO mode only.
rx_out N×J Output Data Receiver parallel data output.
  • DPA-FIFO and non-DPA modes—synchronous to rx_coreclock.
  • Soft-CDR mode—each channel has parallel data synchronous to its rx_divfwdclk.
rx_bitslip_max N Output Control
  • Bit slip rollover signal.
  • High when the next assertion of rx_bitslip_ctrl resets the serial bit latency to 0.
rx_coreclock 1 Output Clock
  • Core clock for RX interfaces provided by the PLL.
  • Not available if you use an external PLL.
rx_divfwdclk N Output Clock

The per channel and divided clock with the ideal DPA phase.

  • This is the recovered slow clock for a given channel.
  • Applicable in soft-CDR mode only.

The rx_divfwdclk signals may not be edge-aligned with each other because each channel may have a different ideal sampling phase. Each rx_divfwdclk must drive the core logic with data from the same channel.

rx_dpa_locked N Output Control

Asserted when the DPA block selects the ideal phase.

  • Driven by the LVDS SERDES IP.
  • Asserts when the signal settles on an ideal phase for that given channel.
  • Deasserts in one of these conditions:
    • The DPA moves one phase.
    • The DPA moves two phases in the same direction.
  • Applicable in DPA-FIFO and soft-CDR modes only.

Ignore all toggling of the rx_dpa_locked signal after rx_dpa_hold asserts.

Table 8.   LVDS SERDES IP TX SignalsIn this table, N represents the LVDS interface width and the number of serial channels while J represents the SERDES factor of the interface.
Signal Name Width Direction Type Description
tx_in N×J Input Data

Parallel data from the core.

tx_out

N Output Data

LVDS serial output data.

tx_outclock

1 Output Clock
  • External reference clock (sent off-chip through the TX data path).
  • Source-synchronous with tx_out.
tx_coreclock 1 Output Clock
  • Drives the core logic feeding the serializer.
  • This signal is a feedthrough of the ext_coreclock input.
Table 9.  External PLL Signals for LVDS SERDES IPFor instructions on setting the frequencies, duty cycles, and phase shifts of the required PLL clocks for external PLL mode, refer to the Clock Resource Summary tab in the IP parameter editor.
Signal Name Width Direction Type Description
ext_fclk 1 Input Clock

LVDS fast clock.

  • Used for serial data transfer.
  • Required in all modes.

For more information about connecting this port with the signal from the IOPLL Intel® FPGA IP, refer to the related information.

ext_loaden

1 Input Clock

LVDS load enable.

  • Used for parallel load.
  • Not required in RX soft-CDR mode.

For more information about connecting this port with the signal from the IOPLL IP core, refer to the related information.

ext_coreclock 1 Input Clock
  • Drives the core logic feeding the serializer (TX) or receiving from the deserializer (RX).
  • Present in RX soft-CDR mode, even though the RX core registers are clocked by rx_divfwdclk.
ext_vcoph[7:0] 8 Input Clock
  • Provides the VCO clocks to the DPA circuitry for optimal phase selection.
  • Required for RX DPA-FIFO and RX soft-CDR modes

For more information about connecting this port with the signal from the IOPLL IP core, refer to the related information.

ext_pll_locked 1 Input Data

PLL lock signal.

Required for RX DPA-FIFO and RX Soft-CDR modes only.
ext_tx_outclock_fclk 1 Input Clock

Phase-shifted version of fast clock

Required for TX outclock phase shifts that are not multiples of 180°
ext_tx_outclock_ loaden 1 Input Clock

Phase-shifted version of load_enable

Required for TX outclock phase shifts that are not multiples of 180°
Related Information
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