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LVDS SERDES Intel® FPGA IP Features
LVDS SERDES IP Core Functional Modes
LVDS SERDES IP Core Functional Description
LVDS SERDES IP Initialization and Reset
LVDS SERDES Intel® FPGA IP Signals
LVDS SERDES Intel® FPGA IP Parameter Settings
LVDS SERDES Intel® FPGA IP Timing
LVDS SERDES Intel® FPGA IP Design Examples
Additional LVDS SERDES IP Core References
LVDS SERDES Intel® FPGA IP User Guide Archives
Document Revision History for LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
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LVDS SERDES IP Core Functional Description
You can configure each LVDS SERDES IP core channel as a receiver or a transmitter for a single differential I/O.
Each LVDS SERDES IP core channel contains a SERDES, a bitslip block, DPA circuitry for all modes, a high-speed clock tree (LVDS clock tree) and forwarded clock signal for soft-CDR mode. Therefore, an n-channel LVDS interface contains n-serdes_dpa blocks.
The I/O PLLs drive the LVDS clock tree, providing clocking signals to the LVDS SERDES IP core channel in the I/O bank.
Figure 1. LVDS SERDES Channel Diagram
Path | Block | Mode | Clock Domain |
---|---|---|---|
TX Data Path | Serializer | TX | LVDS |
RX Data Path | DPA |
|
DPA |
DPA FIFO | DPA-FIFO | LVDS–DPA domain crossing | |
|
|
LVDS | |
Soft CDR | DPA | ||
Clock Generation and Multiplexers | Local Clock Generator | Soft-CDR | Generates PCLK and load_enable in these modes |
SERDES Clock Multiplexers | All | Selects LVDS clock sources for all modes |
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