LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

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ID 683520
Date 9/20/2022
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LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices x
Release Information LVDS SERDES Intel® FPGA IP Features LVDS SERDES IP Core Functional Modes LVDS SERDES IP Core Functional Description LVDS SERDES IP Initialization and Reset LVDS SERDES Intel® FPGA IP Signals LVDS SERDES Intel® FPGA IP Parameter Settings LVDS SERDES Intel® FPGA IP Timing LVDS SERDES Intel® FPGA IP Design Examples Additional LVDS SERDES IP Core References LVDS SERDES Intel® FPGA IP User Guide Archives Document Revision History for LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
LVDS SERDES IP Core Functional Description x
Serializer DPA FIFO Bitslip Deserializer
LVDS SERDES IP Initialization and Reset x
Initializing the LVDS SERDES IP in Non-DPA Mode Initializing the LVDS SERDES IP in DPA Mode Resetting the DPA Word Boundaries Alignment
Word Boundaries Alignment x
Aligning Word Boundaries
LVDS SERDES Intel® FPGA IP Parameter Settings x
LVDS SERDES Intel® FPGA IP General Settings LVDS SERDES Intel® FPGA IP PLL Settings LVDS SERDES Intel® FPGA IP Receiver Settings LVDS SERDES Intel® FPGA IP Transmitter Settings LVDS SERDES IP Core Clock Resource Summary
LVDS SERDES Intel® FPGA IP Receiver Settings x
Receiver Input Clock Parameters Setup
LVDS SERDES Intel® FPGA IP Transmitter Settings x
Setting the Transmitter Output Clock Parameters
LVDS SERDES Intel® FPGA IP Timing x
I/O Timing Analysis FPGA Timing Analysis Timing Analysis when Using PLL Core Clocks Timing Closure Guidelines for Internal FPGA Paths
I/O Timing Analysis x
Obtaining RSKM Report Obtaining TCCS Report
LVDS SERDES Intel® FPGA IP Design Examples x
LVDS SERDES IP Synthesizable Intel® Quartus® Prime Design Examples Generating and Using the Design Example LVDS SERDES IP Simulation Design Example Combined LVDS SERDES IP Transmitter and Receiver Design Example LVDS SERDES IP Dynamic Phase Shift Design Example
Additional LVDS SERDES IP Core References x
IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices LVDS Interface with External PLL Mode LVDS Transmitters and Receivers in the Same I/O Bank Comparison of LVDS SERDES IP Core with Stratix® V SERDES
IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices x
Migrating Your ALTLVDS_TX and ALTLVDS_RX IP Cores
LVDS Interface with External PLL Mode x
IOPLL IP Signal Interface with LVDS SERDES IP IOPLL Parameter Values for External PLL Mode Connection between IOPLL IP and LVDS SERDES IP in External PLL Mode
LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

LVDS SERDES IP Synthesizable Intel® Quartus® Prime Design Examples

The synthesizable design example is a compilation-ready Platform Designer system that you can include in an Intel® Quartus® Prime project.

The design example uses the parameter settings you configured in the IP parameter editor:

  • Basic LVDS SERDES IP system with transmitters or receivers
  • LVDS SERDES IP system with transmitters or receivers connected to an external PLL
Figure 12. Basic LVDS SERDES IP System with Internal PLL


If you configured the IP to use an external PLL, the generated design example connects a properly configured IOPLL Intel® FPGA IP.

Figure 13.  LVDS SERDES IP System with External PLLIn this figure, a qsys_interface_bridge provides Platform Designer connections between the IOPLL IP and the LVDS SERDES IP. For simplicity, this bridge is not shown in the other figures.


To demonstrate how to configure the PLL, the design example also provides the lvds_external_pll.qsys Platform Designer file containing a standalone version of the IOPLL IP configured to work as an external PLL. You can use lvds_external_pll.qsys, modified or unmodified, to build an LVDS design with external PLL.

Generating and Using the Design Example

To generate the synthesizable Intel® Quartus® Prime design example from the source files, run the following command in the design example directory: 

quartus_sh -t make_qii_design.tcl -system ed_synth

The TCL script creates a qii directory that contains the ed_synth.qpf project file. You can open and compile this project in the Intel® Quartus® Prime software.

For more information about make_qii_design.tcl arguments, run the following command: 

quartus_sh -t make_qii_design.tcl -help
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