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Release Information
LVDS SERDES Intel® FPGA IP Features
LVDS SERDES IP Core Functional Modes
LVDS SERDES IP Core Functional Description
LVDS SERDES IP Initialization and Reset
LVDS SERDES Intel® FPGA IP Signals
LVDS SERDES Intel® FPGA IP Parameter Settings
LVDS SERDES Intel® FPGA IP Timing
LVDS SERDES Intel® FPGA IP Design Examples
Additional LVDS SERDES IP Core References
LVDS SERDES Intel® FPGA IP User Guide Archives
Document Revision History for LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
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Deserializer
The deserializer consists of shift registers. The deserialization factor determines the depth of the shift registers. The deserializer converts a 1-bit serial data stream into a parallel data stream based on the deserialization factor.
The load_enable is a pulse signal with a frequency equivalent to the fast clock divided by the deserialization factor.
Figure 3. LVDS x8 Deserializer Waveform
Signal | Description |
---|---|
rx_in | LVDS input data stream to the LVDS SERDES IP core channel |
fast_clock | Clock for the receiver |
load_enable | Enable signal for deserialization |
rx_out[7:0] | Deserialized data |