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Release Information
LVDS SERDES Intel® FPGA IP Features
LVDS SERDES IP Core Functional Modes
LVDS SERDES IP Core Functional Description
LVDS SERDES IP Initialization and Reset
LVDS SERDES Intel® FPGA IP Signals
LVDS SERDES Intel® FPGA IP Parameter Settings
LVDS SERDES Intel® FPGA IP Timing
LVDS SERDES Intel® FPGA IP Design Examples
Additional LVDS SERDES IP Core References
LVDS SERDES Intel® FPGA IP User Guide Archives
Document Revision History for LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
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Timing Analysis when Using PLL Core Clocks
If you use PLL core clocks in your design, the LVDS SERDES IP generation does not create clock settings for the PLL input and output. You must ensure the PLL clock settings are correct.
Some of the SERDES constraints are derived from the PLL clocks. Therefore, the PLL core clock settings must be generated before the LVDS SERDES IP core clock settings. In you project's .qsf, ensure that the line for the IOPLL IP core's .qip appears before the line for the LVDS SERDES IP core's .qip.
Add the following line in your .sdc file to ensure all the PLL clocks are derived correctly.
derive_pll_clocks -create_base_clocks