LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

Download PDF
ID 683520
Date 9/20/2022
Public
Document Table of Contents
Document Table of Contents x
LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices x
Release Information LVDS SERDES Intel® FPGA IP Features LVDS SERDES IP Core Functional Modes LVDS SERDES IP Core Functional Description LVDS SERDES IP Initialization and Reset LVDS SERDES Intel® FPGA IP Signals LVDS SERDES Intel® FPGA IP Parameter Settings LVDS SERDES Intel® FPGA IP Timing LVDS SERDES Intel® FPGA IP Design Examples Additional LVDS SERDES IP Core References LVDS SERDES Intel® FPGA IP User Guide Archives Document Revision History for LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
LVDS SERDES IP Core Functional Description x
Serializer DPA FIFO Bitslip Deserializer
LVDS SERDES IP Initialization and Reset x
Initializing the LVDS SERDES IP in Non-DPA Mode Initializing the LVDS SERDES IP in DPA Mode Resetting the DPA Word Boundaries Alignment
Word Boundaries Alignment x
Aligning Word Boundaries
LVDS SERDES Intel® FPGA IP Parameter Settings x
LVDS SERDES Intel® FPGA IP General Settings LVDS SERDES Intel® FPGA IP PLL Settings LVDS SERDES Intel® FPGA IP Receiver Settings LVDS SERDES Intel® FPGA IP Transmitter Settings LVDS SERDES IP Core Clock Resource Summary
LVDS SERDES Intel® FPGA IP Receiver Settings x
Receiver Input Clock Parameters Setup
LVDS SERDES Intel® FPGA IP Transmitter Settings x
Setting the Transmitter Output Clock Parameters
LVDS SERDES Intel® FPGA IP Timing x
I/O Timing Analysis FPGA Timing Analysis Timing Analysis when Using PLL Core Clocks Timing Closure Guidelines for Internal FPGA Paths
I/O Timing Analysis x
Obtaining RSKM Report Obtaining TCCS Report
LVDS SERDES Intel® FPGA IP Design Examples x
LVDS SERDES IP Synthesizable Intel® Quartus® Prime Design Examples LVDS SERDES IP Simulation Design Example Combined LVDS SERDES IP Transmitter and Receiver Design Example LVDS SERDES IP Dynamic Phase Shift Design Example
Additional LVDS SERDES IP Core References x
IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices LVDS Interface with External PLL Mode LVDS Transmitters and Receivers in the Same I/O Bank Comparison of LVDS SERDES IP Core with Stratix® V SERDES
IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices x
Migrating Your ALTLVDS_TX and ALTLVDS_RX IP Cores
LVDS Interface with External PLL Mode x
IOPLL IP Signal Interface with LVDS SERDES IP IOPLL Parameter Values for External PLL Mode Connection between IOPLL IP and LVDS SERDES IP in External PLL Mode
LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

Comparison of LVDS SERDES IP Core with Stratix® V SERDES

The LVDS SERDES IP core has similar features to the Stratix® V SERDES. The key differences are the clock network and the ubiquitous RX and TX resource in LVDS I/O banks.
Table 25.   Intel® Arria® 10/ Intel® Cyclone® 10 GX and Stratix® V Devices Feature Comparison
Features Intel® Arria® 10/ Intel® Cyclone® 10 GX Devices Stratix® V Devices
Operation Frequency Range 150 MHz - 1.6 GHz1
Serialization/Deserialization Factors 3 to 10
Regular DPA and non-DPA mode Supported
Clock Forwarding for Soft-CDR Supported
RX Resource Every I/O pair

(Every two I/O pairs for CDR)

Every two I/O pairs on every side without HSSI transceivers
TX Resource Every I/O pair Every two I/O pairs every side without HSSI transceivers
PLL Resource TX channels can span three adjacent banks, driven by the IOPLL in the middle bank.

RX channels are driven by the IOPLL in the same bank.

RX and TX channels placed on one edge can be driven by the corner or center PLL.
Number of DPA Clock Phase 8
I/O Standard True LVDS True LVDS, pseudo-differential output
Related Information
1 The supported operation frequency range depends on the device, speed grade, and SERDES factor. Refer to the relevant device datasheet.
Level Two Title