Visible to Intel only — GUID: sam1412833665780
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Release Information
LVDS SERDES Intel® FPGA IP Features
LVDS SERDES IP Core Functional Modes
LVDS SERDES IP Core Functional Description
LVDS SERDES IP Initialization and Reset
LVDS SERDES Intel® FPGA IP Signals
LVDS SERDES Intel® FPGA IP Parameter Settings
LVDS SERDES Intel® FPGA IP Timing
LVDS SERDES Intel® FPGA IP Design Examples
Additional LVDS SERDES IP Core References
LVDS SERDES Intel® FPGA IP User Guide Archives
Document Revision History for LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
Visible to Intel only — GUID: sam1412833665780
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FPGA Timing Analysis
When you generate the LVDS SERDES IP, the IP generates the SERDES hardware clock settings and the core clock for IP timing analysis.
Clock | Clock Name |
---|---|
Core clock | <pll_instance_name>_*_outclk[*] |
LVDS fast clock | <pll_instance_name>_*_lvds_clk[*] |
Clock | Clock Name |
---|---|
Core clock | <lvds_instance_name>_core_ck_name_<channel_num> |
DPA fast clock | <lvds_instance_name>_dpa_ck_name_<channel_num> |
To ensure proper timing analysis, instead of multicycle constraints, the IP creates clock settings at rx_out in the following format:
- For rising edge data— <lvds_instance_name>_core_data_out_<channel_num>_<bit>
- For falling edge data— <lvds_instance_name>_core_data_out_<channel_num>_<bit>_neg
With these proper clock settings, the Timing Analyzer can correctly analyze the timing of the LVDS SERDES–core interface transfer and within the core transfer.