Multi Channel DMA Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683517
Date 7/30/2024
Public
Document Table of Contents

3.3.2. Supported Simulators

The following tables show supported simulators for MCDMA example designs.
Note: Root Port mode MCDMA IP simulation is supported by VCS simulator only.
Note: For 2x8 Hard IP modes, example design simulation is supported on PCIe0 only.
Note: MCDMA R-Tile PIO using Bypass Mode design example simulation is supported for x16 and x8 topologies. The remaining R-Tile design example simulations are not supported. This feature may be supported in a future release of the Quartus® Prime software.
Note: For x4 (1x4 or 2x4 or 4x4) Hard IP modes, example design simulation is not supported.
Table 35.  Supported Simulators for H-Tile MCDMA IP
Tile Design Example User Mode VCS VCS MX Xcelium QuestaSim* Questa* Intel® FPGA Edition Aldec Riviera Pro
H-Tile PIO using Bypass mode

Multi channel DMA

Bursting Master

BAM+BAS

BAM+MCDMA

BAM+BAS+MCDMA

Yes Yes Yes Yes No No
AVMM DMA

Multi channel DMA

BAM+MCDMA

BAM+BAS+MCDMA

Yes Yes Yes Yes No No
Device-side Packet Loopback

BAM + MCDMA

Multi channel DMA

BAM+BAS+MCDMA

Yes Yes Yes Yes No No
Packet Generate/Check

BAM + MCDMA

Multi channel DMA

BAM+BAS+MCDMA

Yes Yes Yes Yes No No
Traffic Generator/Checker

BAM+BAS

Yes Yes Yes Yes No No
Note: SR-IOV simulation support is provided only for 1 physical function and its VFs.
Note: SR-IOV is not supported for simulation in BAM+BAS+MCDMA mode.
Table 36.  Supported Simulators for P-Tile MCDMA IP
Tile Design Example User Mode VCS VCS MX Xcelium QuestaSim* Questa* Intel® FPGA Edition Aldec Riviera Pro
P-Tile PIO using Bypass mode

Multi channel DMA

Bursting Master

BAM+BAS

BAM+MCDMA

Data Mover Only

BAM+BAS+MCDMA

Yes Yes No Yes Yes No
AVMM DMA

Multi channel DMA

BAM+MCDMA

BAM+BAS+MCDMA

Yes Yes No No No No
Device-side Packet Loopback

BAM + MCDMA

Multi channel DMA

BAM+BAS+MCDMA

Yes Yes No No No No
Packet Generate/Check

BAM + MCDMA

Multi channel DMA

BAM+BAS+MCDMA

Yes Yes No No No No
Traffic Generator/Checker BAM+BAS Yes Yes No No No No
External Descriptor Controller Data Mover Only Yes Yes No No No No
Note: SR-IOV is not supported in simulation
Table 37.  Supported Simulators for F-Tile MCDMA IP
Tile Design Example User Mode VCS VCS MX Xcelium QuestaSim* Questa* Intel® FPGA Edition Aldec Riviera Pro
F-Tile PIO using Bypass mode

Multi channel DMA

Bursting Master

BAM+BAS

BAM+MCDMA

Data Mover Only

BAM+BAS+MCDMA

Yes Yes No No No No
AVMM DMA

Multi channel DMA

BAM+MCDMA

BAM+BAS+MCDMA

Yes Yes No No No No
Device-side Packet Loopback

BAM + MCDMA

Multi channel DMA

BAM+BAS+MCDMA

Yes Yes No No No No
Packet Generate/Check

BAM + MCDMA

Multi channel DMA

BAM+BAS+MCDMA

Yes Yes No No No No
Traffic Generator/Checker BAM_BAS Yes Yes No No No No
External Descriptor Controller Data Mover Only Yes Yes No No No No
Note: SR-IOV is not supported in simulation
Note: MCDMA F-Tile 1x4 design example does not support simulation.
Note: F-Tile MCDMA supports PIPE mode simulations.
Table 38.  Supported Simulators for R-Tile MCDMA IP
Tile Design Example User Mode VCS VCS MX Xcelium QuestaSim* Questa* Intel® FPGA Edition Aldec Riviera Pro
R-Tile PIO using Bypass mode

Multi channel DMA

Bursting Master

BAM+BAS

BAM+MCDMA

BAM + BAS + MCDMA

Data Mover Only

Yes Yes No Yes Yes No
AVMM DMA

Multi channel DMA

BAM+MCDMA

BAM + BAS + MCDMA

No No No No No No
Device-side Packet Loopback

BAM + MCDMA

BAM + BAS + MCDMA

Multi channel DMA

No No No No No No
Packet Generate/Check

BAM + MCDMA

BAM + BAS + MCDMA

Multi channel DMA

No No No No No No
Traffic Generator/Checker BAM+BAS No No No No No No
External Descriptor Controller Data Mover Only No No No No No No
Note: SR-IOV is not supported in simulation
Note: MCDMA R-Tile 4x4 PIO using Bypass Mode design example does not support simulation.
Note: Data Mover Only Mode is not available in R-Tile MCDMA IP x4 topology.
Note: The R-Tile design example does not support PIPE mode simulations.