Multi Channel DMA Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683517
Date 7/30/2024
Public
Document Table of Contents

1.2. MCDMA IP Modes

The following table summarizes the MCDMA IP variants, IP mode and FPGA Development Kit board supported for design example hardware test.

Table 2.  MCDMA IP Modes and FPGA Development Kit for Design Examples
MCDMA IP IP Mode FPGA Development Kit Board for Design Example Hardware Test
PCI Express Application Data Width Application Clock Frequency
MCDMA H-Tile Gen3 x16 512 bits 250 MHz

Stratix® 10 GX H-Tile Production FPGA Development Kit

Stratix® 10 MX H-Tile Production FPGA Development Kit

Gen3 x8 256 bits 250 MHz
MCDMA P-Tile Gen4x16 512 bits

Stratix® 10 DX: 400/350/200/175 MHz

Agilex™ 7: 500/450/400/350/250/225/200/175 MHz

Intel Stratix® 10 DX FPGA Development Kit (Production)

Intel Agilex™ 7 FPGA F-Series Development Kit (Production 1 P-Tile and E-Tile)

Gen4 1x8

Gen4 2x8

256 bits

Stratix® 10 DX: 400/350/200/175 MHz

Agilex™ 7: 500/450/400/350/250/225/200/175 MHz

Gen3 x16 512 bits 250 MHz

Gen3 1x8

Gen3 2x8

256 bits 250 MHz
MCDMA R-Tile

Gen5 2x8, Gen4 x16

512 bits

500/475/450/425/400 MHz

Intel Agilex™ 7 FPGA I-Series Development Kit (ES 2 x R-Tile and 1 x F-Tile)

Intel Agilex™ 7 FPGA I-Series Development Kit (ES1 2 x R-Tile and 1 x F-Tile)

Gen4 2x8, Gen3 x16, Gen3 2x8

512 bits

300/275/250 MHz

Gen5 4x4, Gen4 2x8

256 bits

500/475/450/425/400 MHz

Gen3 2x8, Gen4 4x4, Gen3 4x4

256 bits

300/275/250 MHz

Gen4 4x4 128 bits 500/475/450/425/400 MHz
Gen3 4x4 128 bits 300/275/250 MHz
MCDMA F-Tile Gen4 1x16 512 bits 500/400/350/250/225/200/175 MHz

Intel Agilex™ 7 FPGA F-Series Development Kit (ES1 2 x F-Tile)

Gen4 1x8

Gen4 2x8

256 bits 500/400/350/250/225/200/175 MHz
Gen3 1x16 512 bits 250 MHz

Gen3 1x8

Gen3 2x8

256 bits 250 MHz

Gen4 1x4 (Endpoint mode)

128 bits 350/400/450/500 MHz

Gen3 1x4 (Endpoint mode)

128 bits 250 MHz
Note: Intel Agilex™ 7 FPGA I-Series Development Kit (ES 2 x R-Tile and 1 x F-Tile) R-Tile A0 die revision supports only Gen5 2x8 / 512 bit, Gen4 2x8 / 512bits and Gen3 2x8 / 512 bits.
Note: Intel Agilex™ 7 FPGA I-Series Development Kit (ES1 2 x R-Tile and 1 x F-Tile) R-Tile B0 die revision supports all PCIe Hard IP Modes defined in MCDMA R-Tile row

For more information about MCDMA IP, refer to the Multi Channel DMA Intel FPGA IP for PCI Express User Guide.