Multi Channel DMA Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683517
Date 7/30/2024
Public
Document Table of Contents

3.5.2.4.5.4. BAM Test

  1. If the BAM support is enabled on hardware, enable the following flags in: dpdk/dpdk/drivers/net/mcdma/rte_pmd_mcdma.h
    #define IFC_PIO_256 ➤ 256b 
    read/write operations on PIO BAR and undef other size 
    or 
    #define IFC_PIO_128 ➤ 128b 
    read/write operations on PIO BAR and undef other size
  2. Enable the below flag for 256b read or write operations in: dpdk/dpdk/drivers/net/mcdma/rte_pmd_mcdma.h
    #define IFC_PIO_256
    #undef IFC_PIO_128

    Command: ./build/mcdma-test -- -b 0000:01:00.0 -o

  3. Enable the below flag for 128b read or write operations in: dpdk/dpdk/drivers/net/mcdma/rte_pmd_mcdma.h
    #undef IFC_PIO_256
    #define IFC_PIO_128
    
    Command: ./build/mcdma-test -- -b 0000:01:00.0 -o
    Figure 41. PIO 128b Write and Read Test
    Note:
    For BAM_BAS bitstream, undefine IFC_QDMA_INTF_ST
    #undef IFC_QDMA_INTF_ST in dpdk/ dpdk/drivers/net/mcdma/rte_pmd_mcdma.h