Multi Channel DMA Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683517
Date 7/30/2024
Public
Document Table of Contents

3.3.5.3. Steps to Run the Simulation : Xcelium*

Simulation Directory

<example_design>/pcie_ed_tb/pcie_ed_tb/sim/xcelium

Instructions

  1. sh xcelium_setup.sh USER_DEFINED_SIM_OPTIONS="" USER_DEFINED_ELAB_OPTIONS ="-timescale\ 1ns/1ps\ -NOWARN\ CSINFI"
    Note: The simulation command above is a single-line command
  2. Xcelium* simulation command for F-Tile MCDMA IP
    sh xcelium_setup.sh USER_DEFINED_VERILOG_COMPILE_OPTIONS="+define+RTLSIM\ +define+SSM_SEQUENCE\ -sv" USER_DEFINED_ELAB_OPTIONS="-warn_multiple_driver\ -timescale\ 1ns/1ps" USER_DEFINED_SIM_OPTIONS="" | tee simulation.log
    Note: The simulation command above is a single-line command
  3. A successful simulation ends with the following message: "Simulation stopped due to successful completion!"