Multi Channel DMA Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683517
Date 7/30/2024
Public
Document Table of Contents

3.3.5.2. Steps to Run the Simulation : VCS* / VCS* MX

Simulation Directory

<example_design> /pcie_ed_tb/ pcie_ed _tb/sim/synopsys/vcs

<example_design>/pcie_ed_tb/pcie_ed _tb/sim/synopsys/vcsmx

Instructions

Note: Each simulation command below is a single-line command
  1. H/F/P/R Tile VCS:
    sh vcs_setup.sh USER_DEFINED_COMPILE_OPTIONS="" USER_DEFINED_ELAB_OPTIONS="-xlrm\ uniq_prior_final\ +vcs+vcdpluson\ -debug_all" USER_DEFINED_SIM_OPTIONS="" | tee simulation.log
  2. H/F/P/R-Tile VCS MX:
    sh vcsmx_setup.sh USER_DEFINED_COMPILE_OPTIONS="" USER_DEFINED_ELAB_OPTIONS="- xlrm\ uniq_prior_final\ +vcs+vcdpluson\ -debug_all" USER_DEFINED_SIM_OPTIONS="" | tee simulation.log