Multi Channel DMA Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683517
Date 7/30/2024
Public
Document Table of Contents

2.3.2.1. Simulation Results

Testbench writes 4 KB of incrementing pattern to on-chip memory and read back via Avalon-MM PIO interface. This design example testbench doesn’t simulate H2D/D2H data movers.

Figure 3. Simulation Log
Figure 4. Simulation Waveform