Multi Channel DMA Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683517
Date 7/30/2024
Public
Document Table of Contents

2.4.1.3. Hardware Test Result

Note: This test was run with Agilex™ 7 F-Series P-Tile FPGA PCIe Gen4 x16 configuration using Custom Driver.
Note: This test was run with Agilex™ 7 F-Series P-Tile FPGA PCIe Gen4 x16 configuration using CentOS 7 platform.
[root@localhost perfq_app]# ./perfq_app -b 0000:2d:00.0 -p 32768 -l 10 -d 5 -c 8 -a 8 -r
Allocating 8 Channels...

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BDF: 0000:2d:00.0
Channels Allocated: 8
QDepth 508
Number of pages: 8
Completion mode: WB
Payload Size per descriptor: 32768 Bytes
SOF on descriptor: 1
EOF on descriptor: 1
File Size: 32768 Bytes
PKG Gen Files: 64
Rx Batch Size: 127 Descriptors
DCA: OFF
-----------------------------------------------------------------------
Thread initialization in progress ...
Thread initialization done
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Dir  #queues   Time_elpsd     B_trnsfrd      TBW        IBW        MIBW       HIBW       LIBW      MPPS      #stuck
Rx      8       00:05:000     127333248.00KB  24.28GBPS  24.28GBPS  03.04GBPS  03.04GBPS  03.04GBPS 00.80MPPS     0
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All Threads exited
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Dir  #queues   Time_elpsd     B_trnsfrd      TBW        IBW        MIBW       HIBW       LIBW      MPPS      #stuck
Rx      8       00:10:000     251390912.00KB  23.97GBPS  23.66GBPS  02.96GBPS  02.96GBPS  02.96GBPS 00.78MPPS     0
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TIME OUT while waiting for completions
Leaving...
-------------------------------OUTPUT SUMMARY--------------------------------------------
Dir  #queues   Time_elpsd     B_trnsfrd           TBW     MPPS    Passed  Failed  %passed
Rx      8       00:10:871     251390912.00KB   24.29GBPS 00.80MPPS      8      0     100.00%
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Total Bandwidth: 24.29GBPS, 0.80MPPS
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Full Forms:
TBW:            Total Bandwidth
IBW:            Interval Bandwidth
MIBW:           Mean Interval Bandwidth
HIBW:           Highest Interval Bandwidth
LIBW:           Lowest Interval Bandwidth