Multi Channel DMA Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683517
Date 7/30/2024
Public
Document Table of Contents

2.6.2. Hardware Test Results

The Custom Driver was used to generate the following output:
Figure 15. PIO Test-o option
Figure 16. H2D Avalon-MM Write-t option. Note: This hardware test was run with the Stratix® 10 GX H-tile PCIe Gen3 x16 configuration.
Figure 17. H2D Avalon-MM Write Agilex™ 7 F-Series P-Tile PCIe Gen4 x16 The following hardware test was run with Agilex™ 7 F-Series P-Tile PCIe Gen4 x16 configuration using Custom Driver.
Figure 18. H2D Avalon-MM Write with Data Validation Enabled-t -v option. Note: This hardware test was run with the Stratix® 10 GX H-tile PCIe Gen3 x16 configuration.
To enable data validation using -v option, set the software flags in user/common/mk/common.mk as follows:
cflags += -UPERFQ_PERF 
cflags += -DPERFQ_LOAD_DATA
Note: Hardware test with P-Tile Gen4 x16 may be added in a future release.
Figure 19. D2H Avalon-MM Read-r option. Note: This hardware test was run with the Stratix® 10 GX H-tile PCIe Gen3 x16 configuration.
Figure 20. D2H Avalon-MM Read Agilex™ 7 F-Series P-Tile PCIe Gen4 x16