Multi Channel DMA Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683517
Date 7/30/2024
Public
Document Table of Contents

3.5.2.4.5.2. Example of Verifying on an AVMM Design

Modify the below macro in the following file: dpdk/dpdk/drivers/net/mcdma/rte_pmd_mcdma.h

#define PCIe_SLOT 0 /* 0 – x16, 1 – x8 */
Use this command:
Command: $ ./build/mcdma-test -- -b 0000:01:00.0 -p\  
32768 -l 5 -i  -c 2 -d 2 -a 4
Configuration:
  • bdf (-b 0000:01:00.0)
  • 1 channel (-c 2)
  • Loopback (-i)
  • Payload length of 32768 bytes in each descriptor (-p 32768)
  • Time limit set to 5 (-l 5)
  • debug log enabled (-d 2)
  • One thread per queue (-a 4)
Note: Reset the IP before starting DMA by using the following command: ./build/mcdma-test -- -b <bdf> -e