Multi Channel DMA Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683517
Date 7/30/2024
Public
Document Table of Contents

3.5.2.4.5.1. Channel ID VF PF Verification

For Channel ID VF PF verification: Channel ID , VF and PF information is inserted in the AVST/AXIST data pattern. To test dma in a proper channel and VF, it can be tested as described below:

For AVST/AXIST LB

  1. Find the following configuration file
    1. software/dpdk/dpdk/examples/mcdma-test/perfq/meson.build (For Ubuntu)
    2. software/dpdk/dpdk/examples/mcdma-test/perfq/Makefile (For CentOS).
  2. Define the flags: CID_PAT and IFC_PROG_DATA_EN in the configuration files mentioned in the above step.
  3. Define the flag: DCID_PFVF_PAT.
    __cflags += - DCID_PFVF_PAT
  4. Only data validation mode is supported. Performance mode should be disabled.
    __cflags += DPERFQ_LOAD_DATA 
    __cflags += - UPERFQ_PERF
  5. Supported direction: Bi-directional (-i) only.

For AVST PKT GEN

  1. Find the following configuration file
    1. software/dpdk/dpdk/examples/mcdma-test/perfq/meson.build (For Ubuntu)
    2. software/dpdk/dpdk/examples/mcdma-test/perfq/Makefile (For CentOS).
  2. Define the flags: CID_PAT and IFC_PROG_DATA_EN in the configuration files mentioned in the above step.
  3. __cflags += - DCID_PAT 
    __cflags += DIFC_PROG_DATA_EN
  4. Only data validation mode is supported. Performance mode should be disabled.
    __cflags += DPERFQ_LOAD_DATA
  5. Supported directions: Rx, Tx and Bi-directional (-z).