AN 943: Thermal Modeling for Intel® Stratix® 10 FPGAs with the Intel® FPGA Power and Thermal Calculator

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ID 683387
Date 3/29/2021
Public
Document Table of Contents
Document Table of Contents x
1. List of Abbreviations 2. Introduction 3. Intel® Stratix® 10 FPGA Package Mechanical Design 4. Intel® Stratix® 10 FPGA Thermal Design Parameters 5. Thermal Design Process for Intel® Stratix® 10 Devices 6. Power and Thermal Calculator (PTC) for Intel® Stratix® 10 Devices 7. Maximum Power and Typical Power 8. Document Revision History for AN 943: Thermal Modeling for Intel® Stratix® 10 FPGAs with the Intel® FPGA Power and Thermal Calculator
3. Intel® Stratix® 10 FPGA Package Mechanical Design x
3.1. Intel® Stratix® 10 Physical Package Structure
4. Intel® Stratix® 10 FPGA Thermal Design Parameters x
4.1. Intel® Stratix® 10 Compact Thermal Model (CTM) 4.2. Intel® Stratix® 10 Temperature Sensing 4.3. Thermal Sensor Accuracy
6. Power and Thermal Calculator (PTC) for Intel® Stratix® 10 Devices x
6.1. Device Selection 6.2. Logic Design Information 6.3. Thermal Settings and Parameters 6.4. Thermal Design Optimization 6.5. Updating Thermal Parameters 6.6. Intel® Stratix® 10 Device with PCIe Thermal Design Example 1 6.7. Heat Sink 6.8. Intel® Stratix® 10 Device with PCIe Thermal Design Example 2 (Alternate Method)
6.8. Intel® Stratix® 10 Device with PCIe Thermal Design Example 2 (Alternate Method) x
6.8.1. Analyzing 1U Sled with 3 FPGAs
1. List of Abbreviations
2. Introduction
3. Intel® Stratix® 10 FPGA Package Mechanical Design
4. Intel® Stratix® 10 FPGA Thermal Design Parameters
5. Thermal Design Process for Intel® Stratix® 10 Devices
6. Power and Thermal Calculator (PTC) for Intel® Stratix® 10 Devices
7. Maximum Power and Typical Power
8. Document Revision History for AN 943: Thermal Modeling for Intel® Stratix® 10 FPGAs with the Intel® FPGA Power and Thermal Calculator

6.3. Thermal Settings and Parameters

The maximum junction temperature rating of all Intel® Stratix® 10 dies is 100°C unless stated otherwise.

The 1SM21BE device which we are using as the example in this document, is an exception, with a maximum HBM die temperature rating of 95°C. Consequently, for this design we use the Maximum junction temperature mode and set it to 90°C, to provide the design with a margin of 5°C. However, if the analysis indicates that the HBM is not the die with highest temperature, we could then increase the max TJ until the HBM or another die reaches its limit with the margin.

The ambient temperature is set to 50°C.

Many designs utilize both sets of sensors, so temperature offset data from both modes is needed. We also assume that our test project uses both sets of thermal sensors. The figure below shows the PTC Thermal page output and the thermal settings and parameters for the design.

Figure 10. Thermal Settings and Parameters

The die with the highest ΨJC is the die that has the highest temperature and reaches the maximum TJ for the cooling solution calculated by the PTC. In this case the highest ΨJC of 0.103°C/W belongs to HSS_2_1, E tile transceiver tile. With the maximum TJ set to 90°C, the HBM die has a margin of 5°C, calculating the HBM junction temperature.

TJ_HBM = TCASE + TTP x ΨJC_HBM

TJ_HBM = 79 + 105.453 x -0.007 = 78.26

As expected, the above calculations indicate that the HBM die does not have the highest temperature in this design and the maximum TJ can be increased to 95°C if necessary. Doing so also increases the total power to 108 W and ΨCA to 0.312°C/W from the current 0.276°C/W. The higher the ΨCA value, the easier it is to cool the system; however, the total thermal power (TTP) also increases.

The next step in the process is to contact your Intel Field Application Engineer (FAE) to obtain the compact thermal model (CTM) for the device in the format that you need.

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