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1. List of Abbreviations
2. Introduction
3. Intel® Stratix® 10 FPGA Package Mechanical Design
4. Intel® Stratix® 10 FPGA Thermal Design Parameters
5. Thermal Design Process for Intel® Stratix® 10 Devices
6. Power and Thermal Calculator (PTC) for Intel® Stratix® 10 Devices
7. Maximum Power and Typical Power
8. Document Revision History for AN 943: Thermal Modeling for Intel® Stratix® 10 FPGAs with the Intel® FPGA Power and Thermal Calculator
6.1. Device Selection
6.2. Logic Design Information
6.3. Thermal Settings and Parameters
6.4. Thermal Design Optimization
6.5. Updating Thermal Parameters
6.6. Intel® Stratix® 10 Device with PCIe Thermal Design Example 1
6.7. Heat Sink
6.8. Intel® Stratix® 10 Device with PCIe Thermal Design Example 2 (Alternate Method)
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2. Introduction
An Intel® Stratix® 10 device has a multi-chip package structure. It can contain between two and nine dies. One or two dies always comprise the main FPGA core fabric, and there can be from one to six transceiver dies, and up to two High Bandwidth Memory (HBM) dies. Due to complex construction and non-uniform power density of the dies, the thermal engineering of an Intel® Stratix® 10 device requires a specific process and familiarity with the following: