AN 943: Thermal Modeling for Intel® Stratix® 10 FPGAs with the Intel® FPGA Power and Thermal Calculator

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ID 683387
Date 3/29/2021
Public
Document Table of Contents
Document Table of Contents x
1. List of Abbreviations 2. Introduction 3. Intel® Stratix® 10 FPGA Package Mechanical Design 4. Intel® Stratix® 10 FPGA Thermal Design Parameters 5. Thermal Design Process for Intel® Stratix® 10 Devices 6. Power and Thermal Calculator (PTC) for Intel® Stratix® 10 Devices 7. Maximum Power and Typical Power 8. Document Revision History for AN 943: Thermal Modeling for Intel® Stratix® 10 FPGAs with the Intel® FPGA Power and Thermal Calculator
3. Intel® Stratix® 10 FPGA Package Mechanical Design x
3.1. Intel® Stratix® 10 Physical Package Structure
4. Intel® Stratix® 10 FPGA Thermal Design Parameters x
4.1. Intel® Stratix® 10 Compact Thermal Model (CTM) 4.2. Intel® Stratix® 10 Temperature Sensing 4.3. Thermal Sensor Accuracy
6. Power and Thermal Calculator (PTC) for Intel® Stratix® 10 Devices x
6.1. Device Selection 6.2. Logic Design Information 6.3. Thermal Settings and Parameters 6.4. Thermal Design Optimization 6.5. Updating Thermal Parameters 6.6. Intel® Stratix® 10 Device with PCIe Thermal Design Example 1 6.7. Heat Sink 6.8. Intel® Stratix® 10 Device with PCIe Thermal Design Example 2 (Alternate Method)
6.8. Intel® Stratix® 10 Device with PCIe Thermal Design Example 2 (Alternate Method) x
6.8.1. Analyzing 1U Sled with 3 FPGAs
1. List of Abbreviations
2. Introduction
3. Intel® Stratix® 10 FPGA Package Mechanical Design
4. Intel® Stratix® 10 FPGA Thermal Design Parameters
5. Thermal Design Process for Intel® Stratix® 10 Devices
6. Power and Thermal Calculator (PTC) for Intel® Stratix® 10 Devices
7. Maximum Power and Typical Power
8. Document Revision History for AN 943: Thermal Modeling for Intel® Stratix® 10 FPGAs with the Intel® FPGA Power and Thermal Calculator

6.4. Thermal Design Optimization

After you have captured your design in the Intel® FPGA Power and Thermal Calculator (PTC), it is good practice to evaluate whether any thermal optimization is possible to make the cooling easier. Improved cooling can be achieved by reducing overall power consumption, or by reducing the design's ΨJC value.

Power Reduction

There are two types of power consumed in an FPGA: static power and dynamic power.

  • Static power is the power that the configured device consumes when powered up but with no user clocks operating. Static power is dependent on device size, device grade, power characteristics, and junction temperature. For Intel® Stratix® 10 devices, this excludes DC bias power of analog blocks, such as I/O and transceiver analog circuitry.

    Reducing junction temperatures can save power. For example, if a given design has a total static power of 38W when the maximum TJ is 90°C, and you decrease the maximum TJ, the static power also decreases, with no change to the operation of the device. However, reducing the maximum TJ requires additional cooling effects, such as a reduction to the ambient temperature, increased airflow, or the use of a larger heat sink. You should always consider methods of reducing static power consumption—especially when evaluating operating costs for large data centers or central offices.

  • Dynamic power is the additional power consumed due to signal activity or toggling. For example, if you reduce the number of half ALMs or flip flops in the core die, or the clock frequency or toggle rate, the dynamic power goes down. Such action may not always be possible, but you should consider it, especially for dies that seem to be the limiting factor in the cooling system.

Transceiver Channel Spreading

Consider our example, where the Intel® Stratix® 10 device has 3 E-Tile transceivers with 2 of them differing only in channel placement. However, one of those two otherwise-identical E-Tiles has higher thermal resistance and power consumption. The table below depicts this situation.

Table 5.  
Parameter HSSI_2_0 HSSI_2_1
Power (watts) 7.4 7.6
ΨJC °C 0.065 0.103

The HSSI_2_1 tile has all of its 12 active channels physically adjacent to each other, which results in higher power density and makes it more difficult to cool. The higher thermal resistance results in a higher temperature, as calculated below:

∆T= TTP * ∆(Ψjc) =105.5 * (0.103 - 0.065) = 4 °C

It might not be possible to optimize channel placement, depending on the design's constraints and requirements; nevertheless, such optimization should be considered.

For additional information about transceiver layout and channel placement, refer to AN-778 Stratix 10 Transceiver Usage.

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