AN 943: Thermal Modeling for Intel® Stratix® 10 FPGAs with the Intel® FPGA Power and Thermal Calculator

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ID 683387
Date 3/29/2021
Public
Document Table of Contents
Document Table of Contents x
1. List of Abbreviations 2. Introduction 3. Intel® Stratix® 10 FPGA Package Mechanical Design 4. Intel® Stratix® 10 FPGA Thermal Design Parameters 5. Thermal Design Process for Intel® Stratix® 10 Devices 6. Power and Thermal Calculator (PTC) for Intel® Stratix® 10 Devices 7. Maximum Power and Typical Power 8. Document Revision History for AN 943: Thermal Modeling for Intel® Stratix® 10 FPGAs with the Intel® FPGA Power and Thermal Calculator
3. Intel® Stratix® 10 FPGA Package Mechanical Design x
3.1. Intel® Stratix® 10 Physical Package Structure
4. Intel® Stratix® 10 FPGA Thermal Design Parameters x
4.1. Intel® Stratix® 10 Compact Thermal Model (CTM) 4.2. Intel® Stratix® 10 Temperature Sensing 4.3. Thermal Sensor Accuracy
6. Power and Thermal Calculator (PTC) for Intel® Stratix® 10 Devices x
6.1. Device Selection 6.2. Logic Design Information 6.3. Thermal Settings and Parameters 6.4. Thermal Design Optimization 6.5. Updating Thermal Parameters 6.6. Intel® Stratix® 10 Device with PCIe Thermal Design Example 1 6.7. Heat Sink 6.8. Intel® Stratix® 10 Device with PCIe Thermal Design Example 2 (Alternate Method)
6.8. Intel® Stratix® 10 Device with PCIe Thermal Design Example 2 (Alternate Method) x
6.8.1. Analyzing 1U Sled with 3 FPGAs
1. List of Abbreviations
2. Introduction
3. Intel® Stratix® 10 FPGA Package Mechanical Design
4. Intel® Stratix® 10 FPGA Thermal Design Parameters
5. Thermal Design Process for Intel® Stratix® 10 Devices
6. Power and Thermal Calculator (PTC) for Intel® Stratix® 10 Devices
7. Maximum Power and Typical Power
8. Document Revision History for AN 943: Thermal Modeling for Intel® Stratix® 10 FPGAs with the Intel® FPGA Power and Thermal Calculator

4.2. Intel® Stratix® 10 Temperature Sensing

Each die in an Intel® Stratix® 10 FPGA contains at least one digital thermal sensor (DTS) and one temperature sensing diode (TSD). Each DTS has no physical connection to device pins and must be read using temperature sensing software.

For information on temperature sensing software, refer to: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/ug-s10-adc.pdf

The TSDs connect to pins on the device, to which you can connect to read, using external devices such as the Maxim Integrated MAX6581, MAX31730, or Texas Instrument TMP468. Both the DTS and TSD report the temperature of their physical location on the die, which may or may not be the hottest location on the die. For this reason, the PTC adds an offset value to each reading, to correct for the maximum temperature of the corresponding die. The offset values may vary, therefore you must specify which sensors the PTC is to use. (Versions of the PTC earlier than version 20.4 show the DTS offsets; therefore,if you require offset values for the TSDs, you must first port your design to the version 20.4 or later software.

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